Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1999-09-24
2001-04-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C257S074000
Reexamination Certificate
active
06214693
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a process for the production of a semiconductor device, and more specifically to a process for the production of a semiconductor device having a structure in which one gate electrode is formed above a channel-forming region and the other gate electrode is formed below the channel-forming region.
It is known that complete isolation of semiconductor devices can be achieved and “soft error” and a “latch-up” phenomenon which is inherent in CMOS transistors can be prevented by the formation of a semiconductor device in a semiconductive layer formed on an insulating layer. A semiconductor device formed in a semiconductive layer (to be called an “SOI” layer for convenience hereinafter) formed on an insulting layer will be referred to as an SOI (Silicon-On-Insulator) type semiconductor device. It has been studied since a relatively earlier time whether or not high-speed performance and high reliability of a semiconductor device can be accomplished by forming an SOI type semiconductor device (for example, CMOS transistors) in an approximately 0.5 &mgr;m thick SOI layer composed of, for example, silicon.
In recent years, the following has been found. The thickness of the semiconductive layer is adjusted to 100 nm or less, source/drain regions are formed in the entire region of the semiconductive layer in its thickness direction, and a portion of the semiconductive layer below a gate electrode is adjusted to have a relatively low impurity concentration, in order to bring the whole of the portion of the semiconductive layer into a depletion state. In this case, short channel effect can be suppressed, and current driving capacity of the semiconductor device can be improved. Further, high-speed performance of the semiconductor device can be achieved at a low supply voltage, so that a low power consumption can be materialized.
For example, when a MOS type field-effect transistor (to be sometimes referred to as “MOS-FET” hereinafter) is fabricated, one gate electrode is formed above a channel-forming region and the other gate electrode is formed below the channel-forming region, whereby short channel effect can be suppressed, a threshold voltage (V
th
) and “swing” can be controlled, and further, there can be fabricated an X-MOS (MOS-FET which permits concurrent operation of the gate electrodes formed above and below the channel-forming region).
For forming a semiconductive layer on an insulating layer, a SIMOX (Separation by IMplanted OXygen) method or a so-called substrate-bonding method are known, while these methods have their merits and demerits. That is, the SIMOX method is excellent in uniformity of the SOI layer, while it has a defect that flatness of an interface between an insulating layer and a semiconductive layer is not so good. The substrate-bonding method shows excellent flatness of an interface between an insulating layer and a semiconductive layer, while it has a defect that it is difficult to form a uniform semiconductive layer having a particularly thin thickness.
The method of producing a semiconductor device structured to have gate electrodes formed above and below a channel-forming region according to a conventional substrate-bonding method will be explained with reference to
FIGS. 12A
,
12
B,
13
A,
13
B,
14
A,
14
B and
15
hereinafter.
FIGS. 12A
,
12
B,
13
A,
13
B,
14
A,
14
B and
15
show schematic partial cross-sectional views of a silicon semiconductor substrate, and so forth when the silicon semiconductor substrate, and so forth are cut in the length direction of a gate electrode.
[Step-
10
]
First, a convex portion
10
A is formed in a semiconductor substrate
10
composed of a silicon semiconductor substrate by lithography and etching processes. Then, an approximately 50 nm thick first insulating film
121
of SiO
2
is formed on the entire surface by a known thermal oxidation method. Then, a polycrystalline silicon (polysilicon) layer containing an impurity is formed on the entire surface by a known CVD method, and then, the polycrystalline silicon layer is patterned to form a first gate electrode
122
on the convex portion
10
A of the semiconductor substrate
10
. At the same time, a first word line
123
extending from the first gate electrode
122
is formed on the first insulating film
121
. This state is shown in FIG.
12
A. The first insulating film
121
formed on the surface of the convex portion
10
A of the semiconductor substrate
10
also works as a first gate insulating film.
[Step-
20
]
An interlayer
16
is formed on the entire surface by a CVD method, and then the top surface of the interlayer
16
is planarized (see FIG.
12
B). The interlayer
16
may have a two-layered structure, for example, an SiO
2
film and a polycrystalline silicon film formed thereon. The semiconductor substrate
10
and a supporting substrate
17
are bonded to each other through the interlayer
16
(see FIG.
13
A). For example, the bonding is carried out under a condition of an oxygen gas atmosphere at 1100° C. for 30 minutes.
[Step-
30
]
Then, the semiconductor substrate
10
is ground and polished from its rear surface. Specifically, for leaving no grinding damage in the semiconductive layer, first, the semiconductor substrate
10
is mechanically ground with diamond grinding grains from its rear surface until the semiconductor substrate
10
comes to have a thickness of several &mgr;m on the first insulating film
121
(see FIG.
13
B). Then, the semiconductor substrate
10
is selectively polished with a chemical/mechanical polishing method (CMP method) until the bottom
121
A of the first insulating film
121
is exposed. The first insulating film
121
works as a polishing-stop layer, and a semiconductive layer
10
B which is a remaining portion of the semiconductor substrate
10
is left as an SOI layer (see FIG.
14
A).
[Step-
40
]
Then, a sacrificial oxide layer is formed on the surface of the semiconductive layer
10
B by a thermal oxidation method, an ion-implanting mask is formed from a resist material, and the semiconductive layer
10
B is ion-implanted for threshold voltage control. Then, the sacrificial oxide layer is removed with hydrofluoric acid. This state is shown in FIG.
14
B.
[Step-
50
]
Then, a second insulating film i.e., a (second gate insulating film
124
) is formed on the surface of the semiconductive layer
10
B by a thermal oxidation method. Then, a polycrystalline silicon layer containing an impurity is formed on the entire surface by a known CVD method, and the polycrystalline silicon layer is patterned to form a second gate electrode
125
on the semiconductive layer
10
B through the second gate insulating film
124
. At the same time, a second word line
126
extending from the second gate electrode
125
is formed on the first insulating film
121
. This state is shown in FIG.
15
.
In the above-produced semiconductor device, an integration degree thereof can be more significantly improved since it has a structure in which semiconductor device elements are formed below the semiconductive layer
10
B, and the thickness of the semiconductive layer
10
B can be determined with a relatively high degree of freedom since the thickness of the semiconductive layer
10
B can be defined by the height of the convex portion
10
A formed in the semiconductor substrate
10
.
In the semiconductor device produced according to the above steps, the first word line
123
which is an extending portion from the first gate electrode
122
and the second word line
126
which is an extending portion from the second gate electrode
125
face each other through the first insulating film
121
. Generally, the first insulating film
121
has a thickness t
0
(see
FIG. 14A
) of approximately 50 nm when it is formed. In [step-
40
], the sacrificial oxide layer is formed on the surface of the semiconductive layer
10
B, and after ion implantation is carried out, the sacrificial oxide layer is removed
Kananen Ronald P.
Lee Calvin
Rader Fishman & Grauer
Smith Matthew
Sony Corporation
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