Etching a substrate: processes – Planarizing a nonplanar surface
Reexamination Certificate
2001-04-04
2003-02-04
Powell, William A. (Department: 1765)
Etching a substrate: processes
Planarizing a nonplanar surface
C156S345140, C216S088000, C438S692000, C438S745000
Reexamination Certificate
active
06514424
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for the double-side polishing of semiconductor wafers using improved carriers.
2. The Prior Art
A process for the double-side polishing of semiconductor wafers between a plurality of upper polishing heads and a lower polishing plate, which each rotate, is described in U.S. Pat. No. 3,691,694. In this case, one plastic mask per polishing head is used to hold semiconductor wafers, which mask is attached to a guide ring which is separately rotated. E. Mendel and J. R. Hause, in
IBM Technical Report
TR22.2342, presented at the Spring Meeting of the Electrochemical Society in Boston, Mass. on May 10, 1979, propose, for double-side polishing, carriers which are made from fiber-reinforced plastics. These carriers have cutouts for holding semiconductor wafers and external teeth, by means of which they are set in free rotary movement between two polishing plates rotating in opposite directions by an outer ring and an inner ring. There are serious drawbacks to these plastic carriers which are their short service life and the risk of the semiconductor wafers breaking during polishing.
Therefore, carriers made from metal, for example steel, have been developed for double-side polishing. These carriers, in order to protect the edge of the semiconductor wafer, according to an embodiment described in EP 208 315 B1, have plastic-lined cutouts for holding the semiconductor wafers. The linings are secured either by bonding in plastic rings or by injecting plastic into the cutouts and punching out the openings for the semiconductor wafers. Both procedures fail to provide permanent stability of the linings. Plastic linings of this type are even more delicate in long-term use if, in accordance with EP 197 214 A2, they are simply inserted into the cutouts in the carriers.
Further developments of carriers for this application include the incorporation of abrasion-limiting means, for example made from steel or sintered carbides (U.S. Pat. No. 5,422,316), and of parts for dressing or conditioning the polishing cloth during the polishing, for example grinding bodies or brushes (EP 887 152 A2). It is also possible to provide a lining of the cutouts with a profiled device for simultaneous polishing of the edges of the semiconductor wafers (U.S. Pat. No. 5,914,053). In everyday operation, for numerous reasons, for example the occurrence of polishing scratches, the adverse affect on the geometry values of the semiconductor wafers and the lack of stability in long-term use, the use of carriers of this type has proven impossible.
To achieve the high local planarities required for modern processes for the fabrication of electronic semiconductor components, for example the distortion-free application of photomasks, a process for double-side polishing of semiconductor wafers has been developed which is described in German Patent Application Serial Number DE 199 05 737.0 and relates to a tight window of from 2 &mgr;m to 20 &mgr;m for the thickness difference between fully polished semiconductor wafer and carrier. With this process, it is possible to achieve semiconductor wafers with local planarity values, expressed as SFQR
max
for a grid with device areas of 25 mm×25 mm, of less than or equal to 0.13 &mgr;m. These local planarity values are required for semiconductor component processes with line widths of less than or equal to 0.13 &mgr;m. In a preferred embodiment, plastic-lined steel carriers are used.
A drawback which is common to all the processes of the prior art is that it is impossible to fabricate the semiconductor wafers in accurate seuence, as required by the industry. In this context, a person skilled in the art understands the term “fabrication in accurate sequence” to mean that the sequence of wafers produced by sawing a crystal into a multiplicity of semiconductor wafers is maintained during the further processing all the way through to the end product. The practice which is sometimes used of scratching or imprinting identification features into the carriers for double-side polishing has not proven effective, since it leads to local deformation of the carriers. This in turn has the consequence that the geometry of the polished semiconductor wafers, in particular the planarity, is impaired. Also there is a risk of the semiconductor wafers being scratched during the polishing.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a process for the double-side polishing of semiconductor wafers, operating in accurate sequence, with SFQR
max
values of less than or equal to 0.13 &mgr;m, in which carriers with a long service life are used.
The above object is achieved according to the present invention by providing a process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed, and with the semiconductor wafers lying in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers, wherein the set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set, and an item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing.
A significant feature of the invention is that each of the steel carriers, which have been produced in highly planar form, has at least one unambiguous identification feature which allows the semiconductor wafers to be handled in accurate sequence without the polishing results being adversely affected. A further significant feature of the invention is that the plastic linings of the cutouts in the carriers for holding the semiconductor wafers are replaced at fixed intervals, preferably periodically, which considerably increases the service life of the carriers and prevents damage to the edges of the semiconductor wafers.
The starting product for the process is semiconductor wafers which in a known way have been separated from a crystal, edge-rounded and lapped, ground and/or etched. If desired, the edges of the semiconductor wafers may be polished.
The end product of the process is semiconductor wafers which are in the same order as before polishing, satisfy the requirements imposed on semiconductor wafers to be used as starting material for semiconductor component processes with line widths of less than or equal to 0.13 &mgr;m and are superior to the semiconductor wafers produced according to the prior art in terms of their fabrication costs.
The process according to the invention can be used for the double-side polishing of various types of disk-like bodies which consist of a material which can be machined by a polishing process. Examples of materials of this type are glass materials, for example silica-based, and semiconductors, for example silicon, silicon/germanium and gallium arsenide. In the context of the invention, silicon in single-crystal form for further use in the fabrication of electronic components, for example processors and memory elements, is particularly preferred.
The process is particularly suitable for the fabrication of silicon wafers with diameters of greater than or equal to 200 mm and thicknesses of from 500 &mgr;m to 1000 &mgr;m. The semiconductor wafers may either be used directly as starting material for the fabrication of semiconductor components or, after a polishing step has been carried out in order to produce a haze-free surface and/or after the application of layers such as back-surface seals or an epitaxial coating of the wafer front surface and/or after conditioning by a
Altmann Thomas
Heier Gerhard
Wenski Guido
Winkler Wolfgang
Collard & Roe P.C.
Powell William A.
Wacker Siltronic Gesellschaft für Halbleitermaterialien AG
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