Process for sort testing C4 bumped wafers

Details Process for sort testing C4 bumped wafers Process for sort testing C4 bumped wafers

1997-12-31

2000-12-19

Chaudhuri, Olik

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 15, 438613, 438614, H01L 2166, H01L 2144

Patent

active

06162652&

ABSTRACT:
A method of testing an integrated circuit device including depositing a solder bump on a surface of a bond pad on an integrated circuit device, heat treating the solder bump, and testing the integrated circuit device by probing the solder bump.

REFERENCES:
patent: 5341990 (1994-08-01), Nishikawa et al.
patent: 5376584 (1994-12-01), Agarwala
patent: 5492235 (1996-02-01), Crafts et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5651873 (1997-07-01), Uchiyama et al.
patent: 5693565 (1997-12-01), Camilletti et al.
patent: 5756370 (1998-05-01), Farnworth et al.
patent: 5773359 (1998-06-01), Mitchell et al.
patent: 5878943 (1999-03-01), Nishikawa et al.
patent: 5904555 (1999-05-01), Darbha et al.
patent: 5937320 (1999-08-01), Andricacos et al.

Affiliated with

Also associated with

Rating

Process for sort testing C4 bumped wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for sort testing C4 bumped wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for sort testing C4 bumped wafers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-270432