Etching a substrate: processes – Forming or treating electrical conductor article
Patent
1994-12-01
1996-02-20
Dang, Thi
Etching a substrate: processes
Forming or treating electrical conductor article
216 95, 216100, 216101, 216105, 216106, 216108, 216109, 252 792, 252 793, 437183, 1566561, 1566521, H01L 2192
Patent
active
054922356
ABSTRACT:
A method for removing Ball Limiting Metallurgy (BLM) layers from the surface of a wafer in the presence of Pb/Sn solder bumps. In one embodiment, the BLM comprises two layers: titanium and copper. After Pb/Sn solder bumps have been formed over the electrical contact pads of the wafer, the BLM copper layer is etched with a H.sub.2 SO.sub.4 +H.sub.2 O.sub.2 +H.sub.2 O solution. While removing the copper layer, the H.sub.2 SO.sub.4 +H.sub.2 O.sub.2 +H.sub.2 O etchant also reacts with the Pb/Sn solder bumps to form a thin PbO protective layer over the surface of the bumps. When the copper layer has been etched away, the titanium layer is etched with a CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O solution. The PbO layer formed over the surface of the Pb/Sn solder bumps remain insoluble when exposed to the CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O etchant, thereby preventing the solder bumps from being etched in the presence of the CH.sub.3 COOH+NH.sub.4 F+H.sub.2 O etchant. When the titanium etch is complete, the PbO layer is removed from the surface of the Pb/Sn solder bumps by exposing the bumps to a HCl+NH.sub.2 CSNH.sub.2 +NH.sub.4 Cl+H.sub.2 O solution.
REFERENCES:
patent: 5268072 (1993-12-01), Agarwala et al.
patent: 5384283 (1995-01-01), Gegenwarth et al.
Crafts Douglas E.
Lee Caroline S.
Murali Venkatesan
Dang Thi
Intel Corporation
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