Process for selective metal deposition in holes of semiconductor

Details Process for selective metal deposition in holes of semiconductor Process for selective metal deposition in holes of semiconductor

1998-08-25

2000-10-17

Talbot, Brian K.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438672, 438675, 427 97, 427 99, 427282, H01L 2144, B05D 512

Patent

active

061331473

ABSTRACT:
A process for preparing a metallic interconnecting plug in a semiconductor device which comprises the steps of: i) forming an insulating layer on the surface of a semiconductor substrate or a metal underlayer of the semiconductor device, ii) forming a hole in the insulating layer to expose the surface of the semiconductor substrate or the metal underlayer, iii) exposing the surface of the insulating layer to the vapor of a blocking agent under a pressure ranging from 10.sup.-12 to 10 torr for a controlled time period so that a blocking layer is formed only on the outer surface of the insulating layer, the blocking layer not extending over the inside walls of the hole, iv) selectively depositing a conductive metal in the hole using a chemical vapor deposition method to form the metallic interconnecting plug which extends from the surface of the semiconductor substrate or the metal underlayer to the level of the outer surface of the insulating layer, and v) removing the blocking layer from the surface of the insulating layer.

REFERENCES:
patent: 5135779 (1992-08-01), Viehbeck et al.
patent: 5844318 (1998-12-01), Sandhu et al.

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