Process for selective application of solder to circuit packages

Details Process for selective application of solder to circuit packages Process for selective application of solder to circuit packages

1996-04-17

1997-09-30

Niebling, John

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205133, 205146, 22818022, 228254, 437183, H05K 334, C25D 502

Patent

active

056722605

ABSTRACT:
Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

REFERENCES:
patent: 4443304 (1984-04-01), Eidschun
patent: 4861425 (1989-08-01), Greer
patent: 5194137 (1993-03-01), Moore
patent: 5316788 (1994-05-01), Dibble
"Solder Bump-Making Process" IBM Technical Disclosure Bulletin vol. 32, No. 3B, Aug. 1989, New York, pp. 36-37.
"Solder Bump Formation on Via Holes" IBM Technical Disclosure Bulletin vol. 37, No. 6B, Jun. 1994, New York, pp. 299-300.

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