Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1997-02-28
2000-01-11
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438396, 438255, 438253, 438964, H01L 218242
Patent
active
060135557
ABSTRACT:
The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and depositing a layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. A thin layer of amorphous silicon is then formed over the HSG-Si layer. This textured polysilicon structure forms the lower electrode of the DRAM capacitor. A dielectric layer is formed on the lower electrode, and an upper electrode is formed from a second layer of doped polysilicon. As-formed HSG-Si grains tend to form sharp intersections with the polysilicon layers on which they grow. When these HSG-Si grains are exposed to a thermal oxidation environment, poor quality oxides are formed at the sharp corners between the HSG-Si grains and the doped polysilicon layer. The poor quality oxides at the sharp corners between the HSG-Si grains and the doped polysilicon layer break down comparatively readily, and appears to cause leakage currents in capacitors having HSG-Si electrodes. By growing a thin amorphous silicon layer over the surface of the HSG-Si layer, the intersection between the HSG-Si grains and the layer of polysilicon is rounded. Subsequent growth of a thermal oxide, or the formation of other dielectric layers, provides a more reliable capacitor.
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Kao, deceased Chung-Shien
Lur Water
Sun Shih-Wei
Yew Tri-Rung
Jr. Carl Whitehead
Thomas Toniae M.
United Microelectronics Corp.
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