Process for restricting interdiffusion in a semiconductor...

Details Process for restricting interdiffusion in a semiconductor... Process for restricting interdiffusion in a semiconductor...

1999-10-19

2001-07-03

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S178000, C438S590000, C438S592000, C438S593000

Reexamination Certificate

active

06255149

ABSTRACT:

The present invention generally relates to a process for restricting the interdiffusion of silicon and germanium in a semiconductor with composite Si/Si
1−x
Ge
x
, 0<x≦1, gate, such as a CMOS device.
It has been shown that a gate structure including an Si
1−x
Ge
x
layer is an advantageous alternative to PMOS technology.
The reason for this is that the material Si
1−x
Ge
x
, further to having, for equal doping, a lower resistance than polycrystalline silicon, offers the possibility of shifting the threshold voltage of the PMOS device obtained, as a function of the germanium content in the polycrystalline Si
1−x
Ge
x
layer. It can thus be used as a “mid-gap” material in a P
+
gate structure instead of the traditional P
+
/N
+
structure, that is to say, for example for N and P gun transistors with a simple gate containing a polycrystalline Si
1−x
Ge
x
layer with P
+
conductivity.
Further, a gate with a very high concentration of germanium (≧ to 75%) or made of pure germanium also has the advantage of being compatible at the same time for transistors of both types (N and P), which therefore leads to a saving in the technological step (elimination of at least two photolithography steps and, if the layer is doped in situ, of two implantation steps).
For instance, CMOS devices with composite SiGe gate are described in the articles “Symmetric CMOS in Fully Depleted Silicon on Insulator using P
+
Polycrystalline SiGe Gate Electrodes”, Niel KIESTLER and JASON, IEDM 93, pages 727-730, and “A Polycrystalline-Si/Si
1−x
Ge
x
—Gates CMOS technology”, T. KING et al.; IEDM 90, pages 253-256.
A semiconductor device with composite Si/SiGe gate typically includes a silicon oxide layer on a silicon semiconductor substrate, and, on the silicon oxide layer, generally a silicon bonding layer with a thickness less than or equal to 1 nm, and preferably about 0.5 nm, and, on this bonding layer, a polycrystalline Si
1−x
Ge
x
, 0<x≦1, layer with a thickness of as much as 100 nm, but generally with a thickness of the order of 2 to 20 nm.
Above the Si
1−x
Ge
x
layer, there is a silicon layer which may be either amorphous or polycrystalline. The latter layer is necessary because of the very high reactivity of germanium, and therefore of the SiGe alloy, with respect to oxygen and the subsequent difficulty which there is in siliciding the surface of the Si
1−x
Ge
x
layer because of the poor reactivity of germanium and these compounds with the metals used for obtaining metal suicides, such as titanium for example.
Recent studies have shown that, even if the interface between the silicon and Si
1−x
Ge
x
layers were initially indeed plane, abrupt and without roughness, the same was not true after the structure had been annealed, because the interdiffusion of germanium into the encapsulating silicon layer was then observed, principally through the grain junctures of the amorphous or polycrystalline silicon and vice versa, that is to say diffusion of silicon into the SiGe alloy layer through the grain junctions of this layer. The latter point is fundamental because it means that the germanium content of the Si
1−x
Ge
x
layer will be depleted, and the threshold voltage will therefore be modified.
Although the use of amorphous silicon restricts this effect, this limitation of the germanium diffusion is still far from being satisfactory.
It would desirable to provide a process for restricting interdiffusion in a semiconductor with composite Si/Si
1−x
Ge
x
gate which is rapid, industrially applicable, reliable and reproducible.
According to a first embodiment of the process for restricting interdiffusion, a thin layer of amorphous or polycrystalline silicon, typically with a thickness less than 25 nm, preferably between 2 nm and 20 nm, is deposited on the Si
1−x
Ge
x
layer, then this silicon layer is nitrided by bringing the thin layer of amorphous or polycrystalline silicon into contact with the nitric oxide (NO) gas at a pressure of 10
3
to 10
5
Pa and a temperature of 450° C. to 600° C. The encapsulating silicon layer is then deposited in the conventional way.
According to a second embodiment of the process for restricting interdiffusion, a thin layer of amorphous or polycrystalline silicon is deposited on the Si
1−x
Ge
x
layer, as indicated above, then a silicon oxide layer with a thickness less than or equal to 1 nm is formed on the surface of this thin surface layer of silicon before the complementary deposition of silicon is carried out in order to complete the encapsulating silicon layer. The thin silicon oxide layer may optionally be nitrided as described above.


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Zhang et al., “Work Function of Boron-Doped Polycrystalline SixGe1-xFilms,” IEEE Electron Device Letters, vol. 18, No. 9, Sep. 1997, pp. 456-458.
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