Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-26
2001-11-13
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S634000
Reexamination Certificate
active
06316354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for making integrated circuit structures. More particularly, this invention relates to a process for removing a resist mask formed over a low dielectric constant silicon oxide dielectric layer without damaging the low dielectric constant silicon oxide dielectric material.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO
2
) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400° C. to remove moisture.
While the use of the above-described low k silicon oxide dielectric material as a substitute for standard k silicon oxide material results in the desired reduction of capacitance in the resulting integrated circuit structure, such low k silicon oxide dielectric material is more sensitive to other materials and processing than is standard k silicon oxide dielectric material. Because of this, it has been found to be necessary to provide thin barrier layers of conventional (standard k) silicon oxide dielectric material below and above the layer of low k silicon oxide dielectric material. While such barrier layers adequately protect the bottom and top surfaces of the layer of low k silicon oxide dielectric material, subsequent formation of vias, or contact openings, through such low k dielectric material to the underlying conductive portions such as metal lines, or contacts on an active device, exposes further surfaces of the low k silicon oxide dielectric material, i.e., the sidewall surfaces of the vias or contact openings formed through the low k silicon oxide dielectric material.
Exposure of such sidewall surfaces of the via cut through the low k silicon oxide dielectric material can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces. Apparently the presence of carbon or other materials in the low k silicon oxide dielectric material renders the material more susceptible to damage during subsequent processing of the structure. For example, contact openings or vias are usually etched in the low k dielectric layer through a resist mask, following which the resist mask is removed.
Conventionally such via resist mask removal is carried out using an O
2
ashing process which is fast, inexpensive, and easy to handle. However, when such an O
2
ashing process is used to remove a via resist mask used to form vias in low k silicon oxide dielectric material, the oxygen apparently attacks the silicon bonds in the low k dielectric material, e.g., Si—C and Si—H bonds. Thus, when the via resist mask is removed by a conventional ashing process using O
2
, damage can occur to the newly formed and exposed via surfaces of the low k dielectric material resulting in the aforementioned via poisoning, necessitating at least a reduction in the temperature of the ashing process (normally~100° C.). However, even so called mild ashing or oxidizing at about 10° C. is still not completely satisfactory, due to temperature rises in the substrate or wafer as a result of the oxidation which takes place during the process, even when the process temperature is initially low.
U.S. Pat. No. 6,028,015 was issued on Feb. 22, 2000 from copending U.S. patent application Ser. No. 09/281,514 entitled “PROCESS FOR TREATING DAMAGED SURFACES OF LOW DIELECTRIC CONSTANT ORGANO SILICON OXIDE INSULATION MATERIAL TO INHIBIT MOISTURE ABSORPTION”, filed Mar. 29, 1999 and assigned to the assignee of this application. The subject matter of U.S. Pat. No. 6,028,015 is hereby incorporated by reference. In that patent it is proposed to treat such damaged via sidewalls of low k silicon oxide dielectric material, after the via resist mask removal, with either a hydrogen plasma or a nitrogen plasma. Such a treatment with a hydrogen or nitrogen plasma causes the hydrogen or nitrogen to bond to silicon atoms with dangling bonds left in the damaged surface of the low dielectric constant organo silicon oxide insulation layer to replace organo material severed from such silicon stoms at the damaged surface.
U.S. Pat. No. 6,114,259 was issued on Sep. 5, 2000 from copending U.S. patent application Ser. No. 09/362,645 entitled “PROCESS FOR TREATING EXPOSED SURFACES OF A LOW DIELECTRIC CONSTANT CARBON DOPED SILICON OXIDE DIELECTRIC MATERIAL TO PROTECT THE MATERIAL FROM DAMAGE”, filed Jul. 27, 1999 and assigned to the assignee of this application. The subject matter of U.S. Pat. No. 6,114,259 is hereby incorporated by reference. In that patent, it is proposed to prevent degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material by a two step process. First, prior to resist mask removal, the exposed surfaces of a low k carbon doped silicon oxide dielectric material are treated with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material. Then the semiconductor wafer is treated with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer.
It would, however, be desirable to provide a process for removing a via resist mask from a barrier layer formed over a layer of low k silicon oxide dielectric material of an integrated circuit structure without damaging the low k dielectric material, and without the necessity of subjecting the exposed via sidewalls of the low k dielectric material to either a pretreatment to inhibit subsequent damage to the low k dielectric material during the resist removal, or a post treatment to repair damage to the low k dielectric material after the resist removal.
SUMMARY OF THE INVENTION
In accordance with the invention, a process is provided for removing resist mask material from a barrier layer formed over a layer of low k silicon oxide dielectric material of an integrated circuit structure without damaging the low k dielectric material, and without the necessity of subjecting the exposed via sidewalls of the low k dielectric material to either a pretreatment to inhibit subsequent damage to the low k dielectric material during the resist removal, or a post treatment to repair damage to the low k dielectric material after the resist removal. The resist removal process comprises exposing the resist mask material to a hydrogen plasma formed from a source of hydrogen
Collins D. M.
LSI Logic Corporation
Picardat Kevin M.
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