Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1995-08-31
1998-11-03
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438476, 148DIG60, 148DIG147, H01L 21311
Patent
active
058308024
ABSTRACT:
A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.
REFERENCES:
patent: 5364803 (1994-11-01), Lur et al.
patent: 5527718 (1996-06-01), Seita et al.
patent: 5552332 (1996-09-01), Tseng et al.
patent: 5567638 (1996-10-01), Lin et al.
Y.H. Lin, et al., Jpn. J. Appl. Phys., 34 (1/2B)(1995)752, ". . . oxide getterning effect in polys-si gate", Feb. 1995.
Th. Eriksson et al., J. Appl. Phys., 68(5)(1990)2112, "Removal of process-induced fluorine . . . hydrogen-containing atmosphere", Sep. 1990.
M. Fukumoto et al., Appl. Phys. Lett., 50(14)(1987)894, "Fluorine distribution in a CVD WSi/ polycrystalline silicon composite gate structure", Apr. 1987.
S. Wolf, Silicon Processing for the VLSI Era, vol. II, pp. 194-195, 198-199, 397-398, Jun. 1990.
Peter J. Wright et al., "The Effect of Fluorine in Silicon Dioxide Gate Dielectrics", IEEE TED-vol. 36, No. 5, May 1989, pp. 879-889.
Hsing H. Tseng et al., "The Effect of Silicon Gate Microstructure and Gate Oxide Process on Threshold Volt Instabilities in p+ -Gate p-Channel MOSFET's with Fluorine . . . ",IEEE TED vol.39,No.7,pp. 1687-1693.
Paul G.Y. Tsui et al., "Suppression of MOSFET Reverse Short Channel Effect by N20 Gate Poly Reoxidation Process", 1994 IEDM San Francisco, California,Dec. 11-14, pp. 501-504.
S. Kusunold et al., "Hot-Carrier-Resistant Structure by Re-oxidized Nitride Oxide Sidewall For Highly Reliable and High Performance LDD MOSFETS", 1991 IEEE, pp. 25.4.1-25.4.4.
J.D.Hayden, et al., "A High-Performance Quadruple Well, Quadruple Poly BiCMOS Process for Fast 16Mb SRAMs", APRDL, Motorola, Austin, Texas, pp. 1-4.
Maiti Bikas
Tobin Philip J.
Tseng Hsing-Huang
Bowers Jr. Charles L.
Motorola Inc.
Radomsky Leon
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