Process for realizing P-channel MOS transistors having a low thr

Details Process for realizing P-channel MOS transistors having a low thr Process for realizing P-channel MOS transistors having a low thr

1995-06-07

1996-12-31

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257372, 257377, 257379, 257381, 257382, 257402, 257412, H01L 2976

Patent

active

055897010

ABSTRACT:
A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,

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Davari et al., "A High Performance 0.25 .mu.m CMOS Technology", IEEE, Jan. 1988.
Nygren et al., "Dual-Type CMOS Gate Electrodes by Dopant Diffusion from Silicide", IEEE Transactions on Electron Devices, vol. 36, No. 6, Jun. 1989.

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