Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2007-05-15
2007-05-15
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S400000, C713S500000, C713S502000, C713S600000, C702S182000, C700S032000, C700S108000, C700S174000
Reexamination Certificate
active
10837079
ABSTRACT:
A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count in the Icnt Counter is at least IcntMax, then sampling the RTC to obtain a second time T2. T1is then subtracted from T2to obtain a time difference DT which is multiplied by ((1−1/DF)−1) to obtain a Degradation Delay DD period, DF being a constant having a value which is the desired submodel performance with respect to full performance. The Degradation Delay is instituted, the RTC is sampled from time to time to obtain a test third time T3. When a test T3minus T2is not less than DD, then T1is set to T3. Then, the procedure is repeated for a next group of instructions. Optionally, further accuracy can be achieved by treating “wait-type” and/or “RTC-access-type” instructions specially and also by calculating a DDExtra period value which is used to adjust the next DD.
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Bohult Stefan R.
Bull HN Information Systems Inc.
Guenthner Russell W.
Patel Nitin C.
Perveen Rehana
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