Process for producing very narrow buried bit lines for non-volat

Details Process for producing very narrow buried bit lines for non-volat Process for producing very narrow buried bit lines for non-volat

1994-06-13

1999-12-07

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438278, 438251, 438253, 438262, 438595, 438738, H01L 218242, H01L 213205, H01L 21302

Patent

active

05998287&

ABSTRACT:
An improved process of fabricating a read only memory device (ROM's) wherein the buried N+ lines have desirable very narrow widths and are closely spaced. The process provides that masking stripes are formed with vertical sidewalls and that spacers are formed on the sidewalls. The areas between the spacers are filled in. The spacers are etched away to form narrow closely spaced openings. Ions are implanted through the openings to form closely spaced buried lines.

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patent: 5378649 (1995-01-01), Huang
S. Wolf, "Silicon Processing for the VLSIERA", 1986, pp. 285, 286, 290, vol. 1, "Process Technology".

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