Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2002-01-22
2004-04-06
Niebling, John F (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S371000, C438S373000, C438S374000, C438S376000, C438S532000, C438S549000, C438S551000
Reexamination Certificate
active
06716712
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing two adjacent regions of a predetermined area in an integrated semiconductor with different doping, and to an integrated transistor that can be produced using that process. The present invention also relates using the process according to the invention for producing an integrated transistor.
In the production of integrated semiconductor structures, the problem often arises that immediately adjacent regions have to be doped differently. The problem of such different dopings and the solutions that known in the prior art are discussed below using a concrete example of an integrated transistor. However, it goes without saying that the process according to the invention can also be applied to different fields of application in semiconductor production, and is not intended to be restricted to producing integrated transistors.
A bipolar transistor known in the prior art in an integrated semiconductor includes an actual, active transistor. In this case, this includes three adjacent, differently doped areas of semiconductors, the emitter area, the base area and the collector area. Depending on the doping, a distinction is drawn between pnp transistors and npn transistors, the sequence of the letters identifying the sequence of the doping in the emitter, base and collector area.
Furthermore, a transistor arranged in an integrated circuit has further auxiliary structures which surround it and which are used to isolate the potentials and to lead the currents away from the active transistor area. The emitter area is connected, via an emitter contact normally made of polysilicon, to an emitter conductor track, for example made of aluminum. The base area is connected, via a base contact, to a base conductor track. Finally, the collector area is connected, via a so-called “buried layer” which is located underneath the other structures and an intermediate layer and a collector contact, to a collector conductor track. Various silicon oxide isolation layers and spacer insulators are used for electrically isolating the various electrically conductive structures.
The base track resistance, which is the resistance between the base and the base conductor track in bipolar transistors is, in addition to the transit frequency and the base collector capacitance, the critical transistor parameter that determines important characteristics of the transistor such as its maximum oscillation frequency, its gain, its minimum noise its gate delay times, etc. For example, it is true that:
f
max
≈
f
T
8
π
·
R
B
·
C
BC
(
1
)
where:
f
max
is the maximum oscillation frequency,
f
T
is the transit frequency,
R
B
is the base resistance, and
C
BC
is the base collector capacitance;
Or
F
min
≈
1
+
1
β
+
f
f
T
2
·
I
C
V
T
R
B
(
1
+
f
T
2
β
·
f
2
)
+
f
T
2
β
·
f
2
(
2
)
where:
F
min
is the minimum noise figure,
&bgr; is the current gain,
f is the frequency,
f
T
is the transit frequency,
I
C
is the collector current,
V
T
is the thermal voltage, and
R
B
is the base resistance.
In the case of self-adjusting silicon bipolar transistors, the base resistance is substantially composed of three components, which are referred to below as R
B,i
, R
B,e
, and R
B,I
. The inner component R
B,i
arises from the resistance of the base region in the active transistor underneath the emitter area. The external component R
B,e
describes the resistance of the polysilicon track which forms the base contact. R
B,I
constitutes the base resistance that is produced by a low-doped zone under the self-adjusting emitter base insulation, the spacer insulator on the active transistor. This region is referred to generally in the literature as the link region.
In order to reduce the base resistance, optimizations can be carried out on all three areas.
As a result of the progressive lateral scaling of the components, the internal component R
B,i
can be reduced more and more. The external component R
B,e
may likewise be reduced in size by lateral scaling or by using low-resistance materials (for example suicides). The link component therefore increasingly gains in importance for the overall base resistance. In order to reduce the resistance in the link region, it would be expedient to increase the conductivity of the silicon under the spacer by using a deliberate additional base doping.
FIGS. 1A-1D
show the schematic process flow for forming the active base and the link region in the prior art production technologies.
FIG. 1A
shows the initial state of the semiconductor blank before the base doping. The emitter window
1
, which is placed in the area of the subsequent active transistor, is normally structured using a dry etching technique. In addition to the emitter window, further structures of the semiconductor are illustrated, namely two isolation layers
2
and
3
and a polysilicon layer
4
that constitutes the polysilicon track that is formed as an external component of the base of the transistor to be formed. The isolation layer
2
can be applied, for example, using LOCOS (Local Oxidation of Silicon) technology, and the isolation layer
3
can be applied using TEOS technology.
Dopant implantation of the desired dopant is then carried out, as illustrated in
FIG. 1B
by the arrows identified by reference symbol
6
. This leads to base doping
7
a
, which is located in the sub-base of the transistor
5
to be formed. The selected illustrative form of a bar in this case identifies a specific limiting level of base doping. Above the line
7
a
, the doping that is carried out by implantation is higher than a specific limiting level, that is to say a specific limiting concentration within the silicon. Below the line
7
a
, the doping is lower. With suitable selection of the limiting level, it is therefore possible to state, to a first approximation, that the doping reaches as far as the line
7
a
, for example.
The following step performed, during the production of a prior art transistor, is annealing the implantation damage that occurred during the dopant implantation. This annealing is normally carried out by a tempering step, in which the entire wafer is subjected to a defined increase in temperature. In the process, a reduction in the base doping takes place as a result of the outward diffusion of dopant, as illustrated in
FIG. 1C
by the arrow
8
. The reduction in the base doping manifests itself in a shift of the limiting level of the base doping toward the surface, as illustrated by the line
7
b.
A spacer
9
is then deposited onto the silicon exposed in the emitter window. This spacer
9
defines the regions of the base area located below it as link regions. The doping in the active base region and in the link region under the spacer
9
are thus identical in this previously known process.
In the prior art, various processes for increasing the specific base doping under the spacer
9
have already been proposed, and these processes may substantially be divided into two groups. The first group consists of processes having an additional local implantation in the link region, and the second group consists of processes for locally increasing the doping in the spacer area by means of diffusion from highly doped auxiliary layers.
In the case of the first group, the link area is deliberately implanted using conventional processes, by depositing dopants on the link area.
In this process, the active base area has to be covered. Masking with photoresist and using photolithography is not possible in the case of scaled components, because of the small width of the spacer of about only 200 nm. Use is therefore generally made of auxiliary layers, which are structured with self-adjusting processes in order to mask the active base area. The application and structuring of these layers constitutes a significant increase in the process complexity and therefore of the costs.
In addition, the auxiliary layers generally cannot b
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Niebling John F
Pompey Ron
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