Process for producing semiconductor article

Details Process for producing semiconductor article Process for producing semiconductor article

2000-03-21

2001-12-04

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S455000

Reexamination Certificate

active

06326279

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for producing a semiconductor article.
2. Related Background Art
Formation of single-crystal semiconductor layers on insulators is widely known as silicon-on-insulator or semiconductor-on-insulator (hereinafter “SOI”) technique. A large number of researches have been made thereon because the devices utilizing the SOI technique have numerous superior points that can not be achieved by usual bulk silicon substrates on which silicon integrated circuits are to be fabricated. More specifically, the utilization of SOI technique brings about the some advantages, that is, the SOI technique is superior in, e.g., the following points.
(1) It enables high integration with easy separation of dielectrics.
(2) It promises a superior radiation resistance.
(3) Stray capacity can be reduced to enable high-speed performance.
(4) The step of welding can be omitted.
(5) Latch-up can be prevented.
(6) Perfect depletion electric-field effect transistors can be accomplished by thin-film formation.
Among processes for producing SOI silicon wafers, the process as disclosed in U.S. Pat. No. 5,371,037, in which a single-crystal semiconductor layer is formed on a porous layer and this semiconductor layer is transferred to a supporting substrate via an insulating layer, is very superior in view of the advantages such that SOI layers have good film-thickness uniformity, the crystal defect density of SOI layers can be controlled with ease, SOI layers have a good surface smoothness, any specially designed expensive apparatus are not required in its production, and SOI having a film thickness ranging from tens of nanometers to about 10 &mgr;m can be produced using the same apparatus.
In combination with the above process, the process disclosed in U.S. Pat. No. 5,856,229 may be employed, i.e., a process in which, using as a first substrate a substrate having a porous layer, a non-porous single-crystal semiconductor layer is formed on the porous layer, the first substrate is bonded to a second substrate with the former's non-porous single-crystal semiconductor layer facing the latter in contact, thereafter the resultant bonded structure is divided at the porous layer without breaking both the first and second substrates, and the surface of the first substrate is smoothed, on which a porous layer is again formed so that the substrate can be reused. With repetition of this process, the first substrate can be used again and again.
Thus, this process can bring about a great effect that the production cost can greatly be reduced and also the production process itself can be simplified. As methods of dividing the bonded structure without breaking both the first and second substrates, the following methods are available.
They are, e.g., a method in which the bonded structure is pulled in the direction vertical to the bonded surface, a method in which a shear stress is applied in parallel to the bonded surface (e.g., a method in which the respective substrates are moved in the direction opposite to each other at the plane parallel to the bonded surface or a method in which the respective substrates are turned in the opposite directions), a method in which a pressure is applied in the direction vertical to the bonded surface, and a method in which a vibratory energy such as ultrasonic waves is applied to the dividing region.
Also available are a method in which a separating member (e.g., a sharp blade such as a knife) is inserted to the dividing region from the side face of the bonded structure in parallel to the bonded surface, a method in which an expansion energy of a substance made to soak into the porous layer that functions as a dividing region is utilized, a method in which the porous layer that functions as a dividing region is thermally oxidized from the side face of the bonded structure to cause the porous layer to undergo volume expansion to divide the bonded structure, a method in which the porous layer that functions as a dividing region is selectively etched from the side face of the bonded structure to divide the bonded structure, and a method in which a layer capable of producing microcavities formed by ion implantation as the dividing region is used and is heated by irradiation with laser light to divide the bonded structure.
In a prior-art process for producing a semiconductor article by forming a porous layer at the surface of a first substrate, forming a non-porous single-crystal semiconductor film on the porous layer, bonding it to a second substrate, and removing the porous layer so as to transfer the non-porous single-crystal semiconductor film onto the second substrate, the structure of the porous layer formed at the surface of the first substrate relates closely to the number of stacking faults brought into the non-porous single-crystal semiconductor film formed on the porous layer. Accordingly, in order to control the structure of the porous layer, the specific resistance of the first substrate must be controlled.
In general, the stacking faults are said to increase the leak current at p-n junction when metal impurities become deposited at dislocated areas surrounding the stacking faults, to deteriorate the lifetime of minority carriers. Also, there is a possibility of causing the deterioration of breakdown strength of oxide films with the deposition of metal impurities. Accordingly, in putting SOI wafers into practical use, it is an important subject to lower the density of such stacking faults. In particular, the increase in leak current at p-n junction is fatal in the case of bipolar transistors.
In the case of usually available CZ (Czochralski) substrates, however, even in the ingot, its specific resistance is 0.01 to 0.02 &OHgr;·cm, which is seen to be uneven by as much as ±50%. Such uneven specific resistance makes it difficult to control porous structure, and the porous structure greatly affect the density of stacking faults brought into the non-porous single-crystal semiconductor film formed on the porous layer, or the control of structure of high-porosity layers used to divide bonded structures. That is, in the manufacture of SOI wafers, it is important to control their specific resistance stably, but is difficult as long as CZ substrates are used.
As a means for overcoming such a problem, as disclosed in Japanese Patent Application Laid-Open No. 9-102594, a method is available in which elements capable of controlling conductivity type are diffused into a silicon substrate to form a diffused region. In this method, however, the thickness of such a diffused region is controlled chiefly by controlling the temperature and time of heat treatment, and hence the substrate in-plane uniformity of specific resistance and also the specific resistance in the depth direction of the substrate surface may become distributed. Also, the use of CZ substrates leaves problems of swirls and COP discussed below.
In CZ substrates commonly used, swirls and COP are present. Where substrates having COP are used in the manufacture of SOI wafers, this COP, when present in the SOI layer, leads to the formation of defects called HF defects. Silicon is not present at the part of HF defects, and hence such defects are fatal for SOI substrates.
Where swirls caused by uneven density of substrate in-plane impurities are present, the porous structure causes uneven in-plane distribution of porous film thickness when the porous layer is formed. Also, in an attempt to form by diffusion, e.g., a 10
18
/cm
3
-boron-doped layer in a thickness as large as 10 &mgr;m, the boron density reaches 10
19
/cm
3
to 10
20
/cm
3
in the vicinity of the surface in the initial stage of diffusion, so that defects tend to be brought into it.
Accordingly, as a method of controlling the specific resistance of the first substrate, a method is available in which epitaxial silicon is used in the region where the porous layer is formed. Where porous silicon is formed in an epitaxial silicon layer followed by subsequent steps to produce an SOI wa

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