Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2002-02-20
2004-03-23
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S313000, C430S315000, C430S322000, C430S324000, C029S846000, C029S852000, C205S187000, C427S301000, C427S304000
Reexamination Certificate
active
06709803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing a printed wiring board, and particularly to a process for producing a printed wiring board by a so-called full-additive process in which a conductor pattern is additively formed on the surface of an insulating substrate by electroless copper plating.
2. Description of the Prior Art
With the recent development of electronic equipment, electronic components have undergone a significant shift to high density and multifunction, and there is a demand for high-density wiring in printed wiring boards. As a result, a further reduction in line width and line space is required in the printed wiring boards. Under these circumstances, attention is being paid to a process for producing a printed wiring board by additively forming a conductor pattern on the surface of an insulating substrate by electroless copper plating (so-called full-additive process).
A printed wiring board obtained by the full-additive process has a satisfactory dimensional accuracy, as compared with a printed wiring board produced by a conventional process for forming a circuit by plating and etching (subtractive process). Furthermore, the printed wiring board of the circuit of the rectangular section shape obtained by the full-additive process, so that such aboard is suitable for high-density wiring with a narrow line width and space. The dimensional accuracy of a circuit produced by the full-additive process is determined by the dimensional accuracy of a plating resist layer. Therefore, by controlling the dimensional accuracy of the resist layer, a conductive circuit with a high dimensional accuracy can be obtained more easily.
General production steps for a printed wiring board by the full-additive process will be described with reference to
FIGS. 1A
to
1
D. An insulating substrate
102
with an adhesive layer
101
for enhancing plating adhesion formed on the surface of a base substrate
100
such as an epoxy glass substrate or the like is subjected to roughening treatment (
FIG. 1A
) with a roughening solution such as an alkaline permanganate solution. Then, catalyst cores
103
for electroless copper plating are allowed to adhere to the surface of the roughened adhesive layer
101
(FIG.
1
B). Then, regions excluding circuit forming regions are covered with a plating resist
105
having resistance to a plating solution (FIG.
1
C). Thereafter, the entire substrate is soaked in an electroless copper plating solution, whereby a copper plating film is deposited on the regions not covered with the plating resist
105
(i.e., circuit forming regions) by electroless copper plating to form conductive circuits
106
. Thus, a printed wiring board
200
is produced.
In the case where through-holes are required for allowing both sides of the printed wiring board
200
to have electric conductivity, through-holes
104
are formed before roughening the adhesive layer
101
(FIG.
1
B), and the walls of the through-holes
104
are covered with a copper plating film by electroless copper plating simultaneously with the formation of the conductive circuits on the surface of the printed wiring board, whereby copper plated through-holes
107
are formed (FIG.
1
D).
However, in the above-mentioned printed wiring board produced by the conventional full-additive process, the plating catalyst cores
103
are present under the plating resist
105
. Therefore, when the line space becomes smaller than 100 &mgr;m, reliability in electrical insulation between adjacent circuit lines may degrade due to moisture absorption or the like. This is because the catalyst cores present between the lines are ionized with an applied voltage due to moisture absorption and migrate therebetween.
Japanese Patent Application Laid-open No. Sho 62-69696 (hereinafter, referred to as “first prior art technique”) discloses a technique of adding silicone oil or fluorine oil to a plating resist so as to improve water repellent of the resist and suppress adsorption of a catalyst solution (palladium—tin colloid solution) to the resist surface, and selectively forming catalyst cores on the surfaces not covered with the resist (i.e., circuit forming regions). According to this technique, due to water repellent of the plating resist, a catalyst is unlikely to adsorb to the surface of the plating resist. Furthermore, even if a catalyst adsorbs to the surface of the plating resist, the adhesion between the catalyst cores and the plating resist is small, so that the catalyst cores on the plating resist can be easily removed by high-pressure water washing or the like, whereby the insulating property between circuits is enhanced.
Furthermore, Japanese Patent Application Laid-open No. Hei 7-297520 (hereinafter, referred to as “second prior art technique”) discloses a technique of selectively forming catalyst cores on the surfaces not covered with a plating resist, using a copper metal colloid solution. According to this technique, a plating resist is formed on an insulating substrate, and the resultant insulating substrate is treated with a catalyst solution of a copper metal colloid to allow a copper catalyst to adsorb to the surface of the insulating substrate and the surface of the plating resist. Then, the insulating substrate is treated with an alkaline permanganate solution, whereby the copper catalyst adsorbing to the plating resist is removed. A larger amount of copper catalyst adsorbs to the regions not covered with the resist (conductive circuit forming regions), as compared with the regions covered with the resist. Therefore, a portion of copper catalyst remains on the conductive circuit forming regions, without being completely removed with an alkaline permanganate solution. The copper catalyst is likely to be oxidized, so that a Pd catalyst is substituted for the copper catalyst by a substitution reaction with Pd ions. According to this technique, a copper catalyst is not present under the resist, so that the insulating property between circuits is enhanced.
Japanese Patent Application Laid-open No. Hei 6-69632 (hereinafter, referred to as “third prior art technique”) discloses a technique of partially removing Sn of catalyst cores (Pd—Sn) adsorbing to an insulating substrate, forming a plating resist, and forming conductive circuits by electroless copper plating. According to this technique, the insulating substrate is treated with a hydrochloric acid solution or the like so that the Pd concentration of the catalyst cores adsorbing to the insulating substrate becomes 1 to 10 &mgr;g/cm
2
and the Sn concentration thereof becomes 0.1 to 2 &mgr;g/cm
2
, and the concentration of the catalyst cores under the plating resist is controlled, thereby preventing the insulation resistance between circuit lines from being degraded.
However, the above-mentioned first to third prior art techniques have the following problems.
(1) According to the first prior art technique, it is difficult to completely remove catalyst cores from the surface of the plating resist, which makes it difficult to avoid electroless copper deposition onto the surface of the plating resist.
(2) According to the second prior art technique, a copper catalyst in the circuit forming regions is also etched with an alkaline permanganate solution. Therefore, it is required to strictly control the treatment conditions of the alkaline permanganate solution, resulting in poor operability.
(3) According to the third prior art technique, Pd and Sn are present under the plating resist. Therefore, in the case where the line space is 100 &mgr;m or less, the insulating property between circuits is degraded due to moisture absorption.
SUMMARY OF THE INVENTION
Thus, it is an object of the present invention to provide a process for producing a printed wiring board which overcomes the problem regarding the insulating property between circuits of a printed circuit board produced by the above-mentioned conventional full-additive processes.
A process for producing a printed wiring board of the present invent
Barreca Nicole
Huff Mark F.
NEC Toppan Circuit Solutions, Inc.
Young & Thompson
LandOfFree
Process for producing printed wiring board does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for producing printed wiring board, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing printed wiring board will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252463