Process for producing multi-layer wiring structure

Details Process for producing multi-layer wiring structure Process for producing multi-layer wiring structure

1999-09-14

2001-02-20

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S639000, C438S638000

Reexamination Certificate

active

06191031

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a process for producing a multi-layer wiring structure, and more particularly, it relates to a process for producing a multi-layer wiring structure, in which a shape of a contact hole in a so-called dual damascene process is improved.
BACKGROUND OF THE INVENTION
With the increase of minuteness and high-speed operation of an LSI, there are demands of a low resistance of a wiring and a low dielectric constant of an inter level dielectric film. In order to cope with the demands, a copper wiring having a lower resistance than the conventional aluminum alloy wiring, and various organic material f or the insulating film having a lower dielectric constant than the conventional silicon oxide (SiO
2
) film have been investigated to turn them to practical use.
As a technique f or forming a copper wiring, a method using a so-called groove wiring is receiving attention since dry etching of copper is generally difficult. As a technique for forming the groove wiring, a method has been proposed, in which after embedding a wiring material in a contact hole, a groove is formed, and then a wiring material is embedded in the groove (a so-called single damascene process), and furthermore another method has also been proposed, in which both a contact hole and a groove are formed, and then a wiring material is embedded simultaneously in both the contact hole and the groove (a so-called dual damascene process). The dual damascene process has an advantage in cost because an embedding step of a wiring material and a chemical mechanical polishing (CMP) step after the embedding step are conducted only once.
Various methods have been proposed as a method for forming a contact hole and a groove in the dual damascene process. A typical method includes both a method where a groove is formed after forming a contact hole, and a method where a contact hole is formed after forming a groove. In these methods, because a photoresist pattern is formed on a step part, such as the contact hole and the groove having been opened, a problem in defective shape of the photoresist pattern occurs. As an example of a method for solving the problem, a method, in which an etching stop layer having a via hole having been opened therein is embedded, has been proposed. This method will be described with reference to FIGS.
1
(A) and
1
(B).
As shown in FIG.
1
(A), a lower layer copper wiring
112
is formed in a first insulating film
111
to be an insulating film among the lower layer wirings on a substrate
110
. A silicon nitride film as a copper diffusion preventing layer
113
is formed on the lower layer copper wiring
112
and the first insulating film
111
, and then a CVD-SiO
2
film as an insulating film
114
between the wiring layers. A silicon nitride film as an etching stop layer
115
is accumulated. A part of a contact hole
116
is then formed on the etching stop layer
115
by conducting a resist coating step, a lithography step and an etching step.
Thereafter, as shown in FIG.
1
(B), a CVD-SiO
2
film as a second insulating film
117
to be an insulating film among an upper layer wiring is formed on the etching stop layer
115
to fill the contact hole
116
. A resist mask (not shown in the figure) is formed by patterning to form an opening for forming a groove by conducting a resist coating step and a lithography step. A groove
118
is formed in the second insulating film
117
by conducting a reactive ion etching step using the resist mask. Etching is further conducted using the etching stop layer.
115
as an etching mask to complete the contact hole
116
that penetrates the insulating film
114
and the diffusion preventing film
113
, and reaches the lower layer copper wiring
112
.
However, even in the case of the production method according to the conventional technique described above with reference to FIGS.
1
(A) and
1
(B), there is a problem in that the connection hole is liable to have a bowing shape, in which the cross sectional shape largely changes in the depth direction. This is because since the opening area of the connection hole is extremely small in comparison to the opening area of the groove, and when etching of the groove is completed and is switched to etching of the connection hole, radicals in the plasma are concentrated at the connection hole of a small area to cause excessive etching. Furthermore, because the etching rate of the groove becomes uneven within the wafer surface, it is difficult to stably prevent the occurrence of the bowing shape.
SUMMARY OF THE INVENTION
An object of the invention is to provide a process for producing a multi-layer wiring structure that solves the problems described above, the process comprising: a step of forming an inter level dielectric film covering a lower layer wiring; a step of forming a connection hole in the inter level dielectric film to reach the lower layer wiring; a step of forming an inter metal dielectric film filling the connection hole on the inter level dielectric film, with an insulating material having an etching rate larger than that of the inter level dielectric film; and a step of forming a concave part in the inter metal dielectric film, and selectively re-opening the connection hole with respect to the inter level dielectric film in such a manner that the connection hole is continuous to the concave part.
In the process for producing a multi-layer wiring structure of the invention, because only a connection hole is formed in the inter level dielectric film first, the connection hole does not have a bowing shape, in which the cross sectional shape largely changes in the depth direction, but has a shape having a small change in cross section excellent in anisotropy through etching. In the course of forming the concave part and the connection hole in the inter metal dielectric film and the inter level dielectric film, when the etching is switched from formation of the concave part to formation of the connection hole, radicals in the plasma are concentrated to the connection hole of a small area. However, because the inter metal dielectric film filled in the connection hole has a larger etching rate than the inter level dielectric film, i.e., the etching selectivity of the inter level dielectric film is sufficiently large with respect to the inter metal dielectric film, only the inter metal dielectric film filled in the connection hole is selectively etched. Accordingly, the connection hole completed does not have a so-called bowing shape.


REFERENCES:
patent: 5883002 (1999-03-01), Shih et al.
patent: 5924004 (1999-07-01), Hsu
patent: 6027994 (2000-02-01), Huang et al.

Affiliated with

Also associated with

Rating

Process for producing multi-layer wiring structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for producing multi-layer wiring structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing multi-layer wiring structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2573730