Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-19
2004-06-15
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S672000, C438S675000
Reexamination Certificate
active
06750140
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a process for producing contact holes on a metallization structure, which can advantageously be used, for example, to produce electrical contacts between adjacent metallization levels.
During the fabrication of integrated circuits, the electrical lines are generally accommodated in a plurality of metallization levels. The metallization levels are insulated from one another by a dielectric material (“inter layer dielectric”, “ILD”). To provide electrical contacts between the individual metallization levels, contact holes are opened up in the dielectric material and are filled with an electrically conductive material.
FIGS. 3 and 4 of U.S. Pat. No. 6,207,554 describe a process for producing a dielectric layer with a low dielectric constant and then for etching a fully landed contact hole on the interconnects, which are covered with sections of a single-layer or multilayer hard mask. The process for etching the contact hole takes place in two stages, the etching-gas mixtures that are indicated evidently also etch the other layer in each case. It can be seen from FIG. 4
b
of the patent that the contact holes have been etched to beyond the top edge of the interconnects. It is not determined whether the hard-mask layer has been reached in order to then end the first etching step.
U.S. Pat. No. 6,174,800 describes a two-stage etching process in which, during the first etching stage, the contact hole is etched through the dielectric layer, and during the second etching stage, a covering layer that has been applied to the interconnect as an etching stop layer is etched. The second stage is described as sputtering using argon, i.e. not a selective etching process. It is not determined whether the etching stop layer has been reached.
U.S. Pat. No. 5,700,737 discloses a two-stage process for etching a contact hole. The first etching stage takes place selectively with respect to the etching stop layer below it, and consequently, the etching time is not critical. It is not determined whether the hard-mask layer has been reached.
U.S. Pat. No. 4,943,539 describes a process for the two-stage etching of contact holes. In this process, a sacrificial layer, which also serves as an etching stop layer, is additionally arranged above the interconnects and is etched selectively with respect to the interconnects and isotropically, in order to increase the size of the landing area of the contact holes. The second etching step does not take place selectively with respect to the dielectric layer, as shown in FIGS. 3 and 4 of the patent, since back-sputtered material is also removed from the inner surface of the contact-hole in the dielectric layer.
Japanese Patent JP 8-23028 A describes the isotropic etching of a TiN layer that has been applied to an interconnect in order to increase the size of the landing area. It is not determined whether the TiN layer has been reached.
The ongoing miniaturization of the feature sizes and of the integrated circuits gives rise to the general problem that subsequent metallization levels have to be aligned ever more precisely with respect to one another. However, a certain intrinsic misalignment is inevitable when one level is being lithographically mapped onto another. Therefore, the design has to incorporate certain tolerances which ensure that the contacts of one contact hole level can land reliably on the respective interconnects of the metallization level below it. A conventional process for producing a contact hole on a metallization structure is shown, for example, in
FIGS. 2A and 2B
herein.
In
FIG. 2A
, reference numeral
1
denotes an interconnect of a metallization structure, reference numeral
2
denotes remainders of the hard mask that was used to pattern the interconnect, reference numeral
3
denotes the dielectric material for insulating adjacent metallization levels and adjacent interconnects, reference numeral
4
denotes a contact hole, and reference numeral
5
denotes a substrate surface, for example, a processed semiconductor wafer with component and metallization levels that are separated from one another by insulation layers.
As shown in
FIG. 2A
, on account of the misalignment of the etching mask used to etch the contact hole, the contact holes
4
do not land accurately on the interconnects, but rather there is an offset. According to the current state of the art in lithography, there is generally an offset in the region of 40 nm, and in the worst possible scenario the offset may amount to more than 100 nm.
If, as shown in
FIG. 2B
, the contact hole
4
is filled with an electrically conductive material
6
, there is a risk that short circuits will occur between adjacent interconnects.
This drawback has hitherto been minimized by empirically determining the overlap that can be achieved between two lithography levels and taking this overlap into account in the layout of circuit structures, in such a manner that a corresponding metal overlap was observed for an interconnect landing surface of a contact. Hitherto, for a predetermined size of contact hole, the area of the interconnect below it had to be a predetermined amount larger than the landing contact on all sides.
However, this attempted solution cannot be used in conjunction with further miniaturization of the feature sizes, since it predetermines a minimum distance between adjacent interconnects, so that the routing pitch increases. More specifically, to ensure that the distance between the interconnect landing surfaces does not fall below a predetermined distance, it is necessary to maintain a considerable minimum distance between adjacent interconnects.
U.S. Pat. No. 6,015,751 relates to the problem of unlanded contact holes. A metallic layer that is covered with a second dielectric layer is patterned to form interconnects and is covered with a conformally deposited third dielectric layer. Then, a fourth dielectric layer is applied. The contact hole is etched in three stages through each individual dielectric layer, each of the dielectric layers being etched selectively with respect to the adjoining dielectric layers. This process is disadvantageous in that in addition the conformally deposited third dielectric layer is required, in order to prevent the contact hole landing on the first dielectric layer or the contact hole from making contact with adjacent interconnects.
U.S. Pat. No. 5,451,543 also discusses the problem of unlanded contacts. In this document, there is a conformal or non-conformal etching stop layer, which has the disadvantages referred to above. Also, this document does not give any indication of a step of detecting that the hard-mask layer has been reached and ending the first etching stage.
U.S. Pat. No. 5,935,868 likewise describes a process for etching contact holes that are not completely landed on the interconnects.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a process for producing contact holes on a metallization structure which overcomes the above-mentioned disadvantages of the prior art processes of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing contact holes on a metallization structure. The process includes: providing the metallization structure with at least one interconnect having a surface covered with a section of a hard-mask layer and configuring the metallization structure on a substrate surface; applying a dielectric layer so that at least a surface of the section of the hard-mask layer is surrounded by the dielectric layer; forming the dielectric layer from a material that is different than a material of the hard-mask layer; etching contact holes through the dielectric layer; making a determination that the hard-mask layer has been reached; in dependence on the determination, ending the step of etching the contact holes through the dielectric layer; and selectively etching the hard-mask layer with respect to the dielectric layer.
In
Greenberg Laurence A.
Infineon - Technologies AG
Le Dung A.
Locher Ralph E.
Stemer Werner H.
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