Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-30
2001-10-02
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S311000
Reexamination Certificate
active
06297526
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates in general to the field of semiconductors, and specifically to a process for producing an integrated semiconductor memory configuration and to a semiconductor memory configuration produced using the process.
Semiconductor-based memory configurations usually comprise a number of memory cells which each have a selection transistor and a storage capacitor connected to the selection transistor. During a production process for such semiconductor memory configurations, it is usual to apply first electrodes over conductive connections, a respective one of the conductive connections connecting one of the first electrodes to a respective one of the selection transistors. A storage dielectric is applied over the first electrode and in turn has a second electrode applied to it, so that the first and the second electrode as well as the intermediate storage dielectric form a storage capacitor which is conductively connected to one of the selection transistors.
The use of new types of ferroelectric materials as the storage dielectric for storage capacitors allows semiconductor memories to be produced that do not lose their information (stored in the form of electric charge) after a supply voltage failure, and whose memory contents do not have to be refreshed at regular intervals as a result of leakage currents.
A critical factor for the use of most of the previously known ferroelectric materials of this type is their processing within a semiconductor process. Most ferroelectric materials of this type are deposited at high temperatures in an atmosphere containing oxygen. The use of such ferroelectric materials in the process described above, in which the storage dielectric is applied over the first electrode, which in turn is situated above a conductive connection to one of the selection transistors, results in oxidation of the conductive connection because, during deposition of the ferroelectric materials, oxygen diffuses through the first electrode in the direction of the conductive connection and oxidizes the latter. Oxidation of the conductive connection interrupts the electrical connection between the storage capacitor and the selection transistor of a memory cell, with the result being that the latter is no longer functional.
Solutions for preventing oxidation of the conductive connection during deposition of a ferroelectric storage dielectric call for applying barrier layers between the conductive connection and the first electrode, in which case the barrier layers have to be electrically conductive but capable of resisting oxidation and diffusion of oxygen. A disadvantage of the use of barrier layers is that it is hard to find suitable materials that are electrically conductive, impermeable to oxygen, capable of resisting oxidation and that can be suitably applied to the conductive connections.
A process for producing an integrated semiconductor memory configuration having a ferroelectric storage dielectric without using barrier layers is described in U.S. Pat. No. 5,439,840. In this described process, the first electrodes, the storage dielectric and the second electrode are applied over an insulation layer which is situated above selection transistors, using deposition processes. Subsequently, contact holes extending to the selection transistors are produced through the second electrode, the storage dielectric, the first electrode and the insulation layer and can be used to make electrical contact between the second electrode and the selection transistor. The particular disadvantage of this is the complex application of a further insulation layer in the contact hole in order to provide electrical insulation between the first electrode and the second electrode.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a process for producing an integrated semiconductor memory configuration, in which ferroelectric materials are used to produce storage dielectrics for storage capacitors, and in which the use of barrier layers between the conductive connection and the first electrode can be dispensed with, so that the abovementioned disadvantages do not arise, as well as a semiconductor memory configuration produced using the process.
With the foregoing and other objects in view there is provided, in accordance with the invention, a first embodiment of a process for producing an integrated semiconductor memory configuration, which comprises:
providing a configuration of selection transistors having source regions and an insulation layer formed with contact holes extending through to the source regions;
subsequently providing first contact plugs in the contact holes; subsequently applying at least one first electrode on a surface of the insulation layer; and forming the first electrode with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes;
subsequently depositing a dielectric layer on the surfaces of the first contact plugs, the regions of the surface of the insulation layer adjacent the contact holes, and the first electrode;
subsequently depositing a second layer of electrode material on the dielectric layer;
subsequently separating the second layer of electrode material into sections to produce second electrodes;
subsequently exposing the surfaces of the first contact plugs; and
subsequently producing second contact plugs above the exposed first contact plugs electrically connecting a respective one of the second electrodes to a respective one of the first contact plugs.
With the foregoing and other objects in view there is provided, in accordance with the invention, a second embodiment of a process for producing an integrated semiconductor memory configuration, which comprises:
providing a configuration of selection transistors having source regions and an insulation layer formed with contact holes extending through to the source regions;
subsequently providing first contact plugs in the contact holes;
subsequently applying at least one first electrode on a surface of the insulation layer; and forming the first electrode with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes;
subsequently depositing a dielectric layer on the surfaces of the first contact plugs, the regions of the surface of the insulation layer adjacent the contact holes, and the first electrode;
subsequently exposing the surfaces of the first contact plugs; subsequently depositing a second layer of electrode material on the exposed surfaces of the first contact plugs and on the dielectric layer; and
subsequently separating the second layer of electrode material into sections to produce second electrodes.
In accordance with an added feature of the invention, the first electrode application step is performed by depositing a layer of electrode material; and the step of forming cutouts is performed by removing the layer of electrode material from the surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes.
In accordance with an additional feature of the invention, before the first electrode application step, a structured auxiliary layer is applied on the surface of the insulation layer; and the structured auxiliary layer is formed with cutouts exposing surfaces of the first contact plugs and regions of the surface of the insulation layer adjacent the contact holes.
In accordance with an another feature of the invention, a material having ferroelectric properties is selected as the dielectric layer.
In accordance with a further feature of the invention, a material having ferroelectric properties is selected as the dielectric layer.
In accordance with another added feature of the invention, a material having a dielectric constant greater than 10 is selected as the dielectric layer.
In accordance with another additional feature of the invention, a an oxide-containing material selected from the group con
Hintermaier Frank
Mazure-Espejo Carlos
Greenberg Laurence A.
Lerner Herbert L.
Meier Stephen D.
Siemens Aktiengesellschaft
Stemer Werner H.
LandOfFree
Process for producing barrier-free semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for producing barrier-free semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for producing barrier-free semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2568611