Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
1999-05-24
2001-01-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S494000, C438S969000
Reexamination Certificate
active
06171935
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for producing an epitaxial layer with laterally varying doping. The laterally varying doping may, for example, involve a laterally varying doping concentration or, alternatively, a laterally varying doping type, so that n-type doped regions and p-type doped regions alternate with one another in the epitaxial layer.
BACKGROUND OF THE INVENTION
When wishing to obtain layers with varying doping, so-called trench technology has hitherto been employed. However, this technology suffers from unavoidable disadvantages since trenches can economically be formed only to a depth of a few &mgr;m, because it relies on relatively low etching rates for etching the trenches. Etched trenches have very steep side walls and tend to assume a curved shape when a high lateral etching rate is used. This may possibly lead to gaps in the epitaxial layer. Overall, with the conventional process, the production costs are relatively high and the yield leaves much to be desired.
Epitaxial layers with laterally varying doping are, for example, needed for the production of high-voltage MOSFETS, as are described in DE 43 09 764 C2. In this known high-voltage MOSFET, in an inner zone within a space-charge zone that extends in the event of a high threshold voltage, additional zones of conductivity type opposite to that of the inner zone are arranged so that regions with respectively opposite conductivity types alternate with one another in the lateral direction. By virtue of these additional zones, it is possible to provide the MOSFET with a low bulk resistance in the conducting region, even though it has a high threshold voltage.
Satisfactory production of an epitaxial layer with laterally varying doping, that is to say an epitaxial layer in which, for example, p-type conductivity regions and n-type conductivity regions alternate with one another laterally, has not yet satisfactorily been achieved.
It is desirable to have a process for producing an epitaxial layer with lateral varying doping. It is also useful that the angle of inclination of the interfaces between the differently doped regions of the epitaxial layer be controlled.
SUMMARY OF THE INVENTION
The present invention is directed to a process for forming on a top surface of a semiconductive body an epitaxial semiconductive layer whose conductivity characteristics vary laterally across the surface. The process comprises the steps of: (a) applying a patterned insulator layer to a semiconductor body of one conductivity type; (b) growing a first epitaxial layer of the one conductivity type or of the conductivity type, on the semiconductor body and the patterned insulator layer so that monocrystalline regions are created over the semiconductor body and polycrystalline regions are created over the patterned insulator layer, the angle of inclination of the interface, between the monocrystalline regions and the polycrystalline regions, extending essentially perpendicular to the surface of the semiconductor body and depending on the grain size of the polycrystalline silicon of the polycrystalline regions; (c) removing the polycrystalline regions and the patterned insulator layer, and (d) growing a second epitaxial layer with a conductivity type that is either opposite to the conductivity type of the first epitaxial layer, or with the same conduction type but with a different doping concentration, on the semiconductor body in the eroded polycrystalline regions in order, together with the monocrystalline regions of the first epitaxial layer, to form the epitaxial layer.
The process according to the invention thus firstly uses the fact that a polycrystalline silicon layer is formed on an insulator layer, for example, a silicon dioxide layer, if the epitaxy is carried out in an appropriate manner. At the same time, however, a monocrystalline layer is created over the regions of the semiconductor body that are free of the insulator layer, since the epitaxial layer can grow here on the monocrystalline material of the semiconductor body.
The polycrystalline silicon layer grows depending on the original crystal orientation, either wider or narrower, as its thickness increases. By virtue of this, it is thus possible to adjust the angle of inclination of the interfaces between the different regions of the first epitaxial layer by means of the grain size of the polycrystalline material. This grain size is customarily controlled by the deposition technique.
If desired, it is possible to also use the insulator layer as a mask, for example, in ion implantation, to introduce an impurity into the semiconductor body at targeted locations to change the conduction properties of the implanted regions.
Following the epitaxial deposition of the first epitaxial layer, the polycrystalline silicon regions are removed, for example by selective etching. As an alternative, the removal of the polycrystalline may also be carried out by etching along an expected boundary between the moncrystalline and polycrystalline edge down to the insulator layer, the insulator layer then acting as an etch stop. For etching the polycrystalline regions, use may be made of the fact that the doping of polycrystalline silicon takes place substantially more rapidly than the doping monocrystalline silicon.
After the polycrystalline regions and underlying patterned insulator layer have been removed, a second epitaxial layer is deposited. It likewise grows in monocrystalline fashion on the underlying semiconductor body. This second epitaxial layer may have the same conductivity type as the first epitaxial layer or, alternatively, the conductivity type opposite to this. Furthermore, one of the two epitaxial layers is preferably doped in the opposite type to the underlying semiconductor body. It is, however, also possible to provide both epitaxial layers with the same conductivity type, so that the first epitaxial layer differs from the second epitaxial layer merely by a different doping concentration instead of a different conductivity type. It will be convenient to describe a difference in either the conductivity type or a doping concentration generally as a difference in conduction characteristics.
In order to produce the high-voltage MOSFET described in DE 43 09 764 C2, a p-type conductivity epitaxial layer is firstly applied, for example, to an n-type conductivity doped wafer. This is followed by the production of a patterned insulator layer of, for example, silicon dioxide on this p-type conductivity epitaxial layer.
Next, the first epitaxial layer is deposited. This layer grows in monocrystalline fashion on the semiconductor body itself and in the polycrystallone fashion on the insulator. The polycrystalline regions formed in this wasy, and the underlying parts of the insulator layer, are removed. This is followed by further epitaxy, in which a second n-type conductivity epitaxial layer is applied in the regions on the semiconductor body that had previously been cleared of the polysilicon layer and the insulator layer. This second epitaxial layer therefore grows in monocrystalline fashion in the said regions, so that overall an epitaxial layer is obtained in which the p-type conductivity regions and n-type conductivity regions alternate with one another in the lateral direction. The second epitaxial layer may in this case be grown with a layer thickness such that it covers the monocrystalline regions of the first epitaxial layer. This means that, if the conductivity type of the first and second epitaxial layers are different, then for example all n-type conductivity regions, which are formed by the first epitaxial layer, are doped from the rear of the wafer, while all p-type conductivity regions of the second epitaxial layer, are connected to one another on the front of the wafer. In this case, the underlying pattern is still visible and can be used for alignment purposes. Contact may be made with the first and second epitaxial layers in the usual way, as for example, as with a DMOS transistor.
Viewed from on aspect, the present invention is
Nance Paul
Werner Wolfgang
Estrada Michelle
Fourson George
Ostroff Irwin
Siemens Aktiengesellschaft
Torsiglieri Arthur J.
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