Process for producing a semiconductor device

Details Process for producing a semiconductor device Process for producing a semiconductor device

1999-08-25

2001-05-22

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000

Reexamination Certificate

active

06235629

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 10(1998)-274866 filed on Sep. 29, 1998, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for producing a semiconductor device, particularly a semiconductor device having a plurality of wiring layers.
2.Description of Related Art
A first conventional process for forming a multiple-layered interconnect is shown in FIGS.
2
(
a
) to
2
(
c
). As shown in FIGS.
2
(
a
) and
2
(
b
), an insulating film
29
is formed on a patterned wiring layer
28
formed of an aluminum alloy film on an interlayer dielectric film
24
. Thereafter, the insulating film
29
is flattened by a technique such as a chemical mechanical polishing method (hereinafter, referred to as CMP method), and subsequently a through hole is formed. A barrier metal layer
30
and an electrically conductive film
31
which are to form an upper wiring layer are formed on the insulating film
29
and patterned, as shown in FIG.
2
(
c
). By repeating the above-mentioned process, the multiple-layered interconnect structure is formed.
If the aspect ratio of the through hole is high, tungsten is buried in the opening of the through hole by a CVD method and then etched back to form a tungsten plug. Thereafter, the upper wiring layer is formed.
In this process of forming the insulating film
29
after the wiring layer
28
is formed, if a wiring pitch is small, it is difficult to bury the insulating layer
29
between the wiring layers
28
. Further, it is difficult to form the upper wiring layer because the resulting surface after the formation of the insulating film
29
is formed is so rough.
For these reasons, Japanese Unexamined Patent Publication No. HEI 7(1995)-153757 proposes a process of forming a through hole and a trench for wiring in the insulating film and subsequently filling them with a material for wiring, as in the following second conventional art.
The second conventional process for forming a multiple-layered interconnect is shown in FIGS.
3
(
a
) to
3
(
c
). As shown in FIG.
3
(
a
), a trench for wiring is formed in an insulating film
32
formed thick on an underlying wiring layer
28
. Next, a through hole is formed with use of a through hole pattern mask
33
which is formed on the insulating film
32
, as shown in FIG.
3
(
b
). Thereafter a barrier metal layer
30
and an electrically conductive film
31
are formed as materials for wiring in the wiring trench and the through hole, and an unnecessary part of the materials for wiring is removed by a CMP method for flattening. Thus an buried wiring layer is formed, as shown in FIG.
3
(
c
).
In FIGS.
3
(
a
) to
3
(
c
), the through hole is formed after the wiring trench is formed. However, the through hole may be first formed, before the formation of the wiring trench and the subsequent burying of the materials for wiring.
However, in this process of forming the wiring trench and the through hole in the insulating film and afterward burying the wiring materials therein, it is difficult to control the depth of wiring trenches because of variations in etching within a wafer and because of variations in etch depth caused by various widths of wiring trenches. As a result, the depth of the wiring trenches varies greatly. This variation leads directly to variations in the thickness of the wiring layers. consequently, there is a problem that resistance varies greatly among the wiring layers.
As means to solve this problem, Japanese Unexamined Patent Publication No. HEI 8(1996)-17918 proposes a process of providing an etching stop layer in the middle of the insulating film as in the following third conventional art.
The third conventional process for forming a multiple-layered interconnect is shown in FIGS.
4
(
a
) to
4
(
c
). As shown in FIG.
4
(
a
), an insulating film
29
of a SiO
2
film and an etching stop layer
34
of a SiN film are formed on an underlying wiring layer
28
. Subsequently the etching stop layer
34
is removed from a region where a through hole is to be formed, by etching using a resist film as a mask. After the resist film is removed, an insulating film
35
is formed and a resist layer
36
with a wiring pattern is formed as shown in FIG.
4
(
b
). When the insulating films
35
and
29
are etched using this resist layer
36
as a mask, etching stops at the etching stop layer
34
in a region of a wiring trench and proceeds to the underlying wiring layer
28
in the region of the through hole. Subsequently, the resist layer
36
is removed, and a barrier metal layer
30
and an electrically conductive film
31
are formed as materials for wiring in the wiring trench and the through hole. An unnecessary part of the materials for wiring is removed by a CMP method for flattening. Thus a buried wiring layer is formed as shown in FIG.
4
(
c
). According to this process, the depth of wiring trenches is uniform, and buried wiring layers of uniform resistance can be obtained.
Additionally, in FIGS.
2
(
a
) to
2
(
c
),
3
(
a
) to
3
(
c
) and
4
(
a
) to
4
(
c
), there are also shown a semiconductor substrate
21
, a device isolation region
22
, a diffusion layer
23
, an interlayer dielectric film
24
, a barrier metal layer
25
, a contact plug
26
, a barrier metal layer
27
, a wiring layer
28
, an insulating film
29
, a barrier metal layer
30
, an electrically conductive layer
31
, an insulating film
32
, a through hole pattern mask
33
, an etching stop layer
34
, an insulating film
35
and a resist layer
36
.
The above-described process of providing the etching stop layer in the middle of the insulating film can eliminate variations in the resistance of the wiring layers. However, when the through hole is formed, the upper insulating layer
35
has already been formed. Accordingly, the aspect ratio of the through hole is high, which results in a difficult patterning. Also there is a problem that oxygen generated while the lower insulating film
29
is etched decreases the selective ratio of the insulating layer to the etching stop layer.
Further, as more and more highly semiconductor devices are integrated, the wiring density increases and therefore the capacitance produced between wires rises, which affect fast operation adversely. For this reason, insulating films having low dielectric constants are now being studied instead of conventional insulating films made of oxides. SiOF films which are fluorinated oxide films are known as such insulating films, but the dielectric constants of the films are not sufficiently low. Accordingly, films of carbon-base synthetic resins are being developed instead of silicon-base films recently. Such films, however, are etched at the same time as the resist mask is removed if they are used in the process shown in FIGS.
4
(
a
) to
4
(
c
). As a result, at ashing after the insulating film at the through hole region is etched, the synthetic resin films in the wiring trench region are greatly etched in a lateral direction. For this reason, the combination of the process of FIGS.
4
(
a
) to
4
(
c
) and a synthetic resin film has not been suitable for high integration.
SUMMARY OF THE INVENTION
The present invention provides a process for producing a semiconductor device comprising the steps of forming a first insulating film on an underlayer having an electrically conductive layer; forming a first opening in the first insulating film to expose at least a part of the electrically conductive layer; forming on the first insulating film a second insulating film which is more susceptible to etching than the first insulating film while filling the first opening with the second insulating film; forming a mask having an opening at least as large as the first opening in a region on the second insulating film which region corresponds to the first opening; removing at least the second insulating film filling the first opening with use of

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