Process for producing a bipolar transistor with self-aligned...

Details Process for producing a bipolar transistor with self-aligned... Process for producing a bipolar transistor with self-aligned...

2001-01-19

2002-10-15

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S366000

Reexamination Certificate

active

06465317

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 0000791, filed on Jan. 21, 2000, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of manufacturing bipolar transistors, and more particularly to a process for manufacturing a bipolar transistor with an emitter that is self-aligned with respect to an extrinsic base of the transistor, such as for a heterojunction bipolar transistor.
2. Description of the Prior Art
Conventionally, the fabrication of a bipolar transistor comprises the following successive steps:
the production in a semiconductor substrate, for example a p-type silicon substrate, of a buried extrinsic collector layer, for example a layer n
+
-doped by arsenic implantation;
the production on either side of the extrinsic collector of two buried isolation layers, for example p
+
-doped by boron implantation;
the production by thick epitaxy, on the substrate thus formed, of a layer of single-crystal silicon, for example of the n type;
the production in the thick single-crystal silicon layer of a lateral isolation region, either by a local oxidation (LOCOS) process or one of the “shallow trench” type, in order to define an intrinsic collector region in the thick silicon layer;
the production of a collector well, for example n
+
-doped, especially by phosphorus implantation, which contacts the buried extrinsic collector layer;
the production under the lateral isolation region of wells, for example p-doped by boron implantation, in order to isolate the bipolar transistor from the adjacent transistors;
the formation of a thin layer of thermal oxide, typically SiO
2
, on the surface of the intrinsic collector region;
the formation of an amorphous silicon layer on the surface of the thermal oxide layer and of the lateral isolation region;
the plasma etching in the amorphous silicon layer of a window called a “base window”, which etching stops on the thermal oxide layer;
the chemical deoxidation of the thermal oxide layer laying above the intrinsic collector region and exposed by the base window;
the formation by non-selective epitaxy of a layer, typically an Si/SiGe alloy/Si three-layer stack, in which the future intrinsic base of the transistor will be produced;
the formation, on the stack of the intrinsic base, of an insulation layer by depositing tetraethylorthosilicate (TEOS) and then by depositing a nitride layer;
the production by means of a resin mask, on the layer for forming the intrinsic base, in the insulation layer, of an emitter window lying above the intrinsic collector region;
the production of a polycrystalline silicon (polysilicon) emitter by chemical vapor deposition and etching by means of a photolithography mask;
the formation of the extrinsic base and the connection contacts. Such a conventional process for fabricating a bipolar transistor is described, among others, in French Patent No. 98/07059.
One drawback with the conventional processes, like that which has just been described, is that they require the use of at least three masks. This multiplicity of masking, because of the tolerances, does not allow self-alignment of the extrinsic base and the emitter to be obtained. This lack of self-alignment is further aggravated by the density and the dimensions desired for the apertures (windows).
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above, and more specifically for a process for producing a bipolar transistor that remedies the drawbacks of the processes in the prior art.
SUMMARY OF THE INVENTION
A preferred embodiment of the present invention comprises a process for producing a bipolar transistor allowing self-alignment of the extrinsic base and the emitter.
A significant advantage of the invention is that the process for producing a bipolar transistor, according to a preferred embodiment of the present invention, requires two masking steps instead of the usual three.
Preferably, the process produces a bipolar transistor while reducing the problems associated with the density and the dimensions of the apertures (windows).
According to the invention, the process for producing a bipolar transistor, the emitter of which is self-aligned with the extrinsic base, comprises the following steps:
the production of a structure comprising a semiconductor substrate in which an extrinsic collector, insulating layers of the extrinsic base, a lateral isolation region and an intrinsic collector region are formed, the said structure having a main surface on which an amorphous silicon layer, defining a base window in the intrinsic collector region, and a layer that will form the future base of the transistor and covering the amorphous silicon layer and the base window, are deposited,
the successive deposition, on the layer that will form the future base of the transistor, of an SiGe alloy layer, a thin silicon oxide layer and a silicon nitride layer;
the etching by means of a mask of the silicon nitride layer, the silicon oxide layer and the SiGe alloy layer in order to form, on the layer that will form the future base of the transistor, above the intrinsic collector region, a false emitter of geometry and dimensions corresponding to the desired geometry and dimensions of the final emitter;
the formation of spacers on the two opposite sides of the false emitter;
the formation of an extrinsic base region in the layer that will form the future base of the transistor;
the formation of a metal silicide layer on the extrinsic base region;
the deposition of a thick silicon dioxide layer so as to cover the metal silicide layer and the false emitter;
the chemical-mechanical polishing of the thick silicon dioxide layer down to the level of the false emitter;
the etching of the false emitter layers in order to form an emitter window;
the deposition of a polysilicon layer filling the emitter window and covering the thick silicon dioxide layer; and
the etching, by means of a mask, of the polysilicon layer in order to complete the emitter.
The process according to a preferred embodiment of the present invention comprises only two masking steps, for the etching of the false emitter and the final etching of the emitter.
The operations of depositing the SiGe alloy, silicon oxide and silicon nitride layers, and the operations of etching these layers, are conventional and well known in the art.
For example, the SiGe alloy layer may be deposited by non-selective epitaxy. Preferably, the SiGe alloy has a high germanium content, typically 15 to 50%, and preferably 20 to 50%, the etching selectivity with respect to silicon increasing with the germanium content. The thickness of the SiGe alloy layer is generally about 20 to 50 nm.
The thin oxide layer may be deposited by plasma-enhanced chemical vapor deposition (PECVD) using an alkyl silicate such as tetraethylorthosilicate (TEOS). This layer generally has a thickness of 30 to 40 nm.
The silicon nitride layer may be formed in a conventional manner by PECVD deposition. This silicon nitride layer must have a thickness corresponding to the desired thickness of the final polycrystalline silicon (polysilicon) emitter. This thickness, in the case of a BiCMOS structure, must also be sufficient to take into account the gate thickness and the subsequent chemical-mechanical polishing. In general, the thickness of the silicon nitride layer is from 200 to 300 nm, typically about 250 nm.
The operations of etching the silicon nitride, silicon oxide and SiGe alloy layers in order to form the stack forming the false emitter, and the operation of etching these same layers in the stack of the false emitter, may be carried out by any conventional process well known in the art. This etching may be carried out using a plasma, for example an NF
3
/He gaseous plasma. Lateral overetching of the SiGe alloy layer is possible depending on the final dimensions of the emitter and on the above photol

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