Process for preparing solderable integrated circuit lead frames

Details Process for preparing solderable integrated circuit lead frames Process for preparing solderable integrated circuit lead frames

1994-06-16

1995-10-03

Niebling, John

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205122, 205129, 205176, 205181, C25D 502, C25D 510, H01L 2350

Patent

active

054549299

ABSTRACT:
A process for preparing a solderable lead frame from a copper base lead frame is disclosed using plating of tin or tin alloys followed by plating of palladium. Preferably, the tin plating is a spot plating to deposit tin only on the external leads and the palladium plating is a flood plating to deposit palladium over the entire lead frame. A diffusion barrier, preferably of cobalt or nickel, can be applied by plating the base lead frame before tin plating.

REFERENCES:
patent: 4404079 (1983-09-01), Jahani
patent: 4404080 (1983-09-01), Jahani
patent: 4405432 (1983-09-01), Kosowsky
patent: 4486511 (1984-12-01), Chen et al.
patent: 4628165 (1986-12-01), Nobel et al.
patent: 4888449 (1989-12-01), Crane

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