Fishing – trapping – and vermin destroying
Patent
1993-07-09
1996-04-09
Fourson, George
Fishing, trapping, and vermin destroying
437247, H01L 21322
Patent
active
055061540
DESCRIPTION:
BRIEF SUMMARY
INDUSTRIAL FIELD OF THE INVENTION
This invention relates to a process for manufacturing semiconductor devices, and more particularly to a technique in which there is taken advantage of a relationship among the initial oxygen concentration (hereinafter called initial Oi) of a water, the SORI of the wafer in heat treatment process, and the Bulk Micro Defect density (hereinafter called BMD density), to limit, to the minimum extent the SORI of the wafer, which is caused by the heat treatment subjected to during the manufacturing process of elements and to retain the BMD density required for a gettering action whereby the device yield is improved.
PRIOR ART
In manufacturing semiconductor elements using a silicon single crystal as a substrate a variety of gettering methods have been conventionally developed and used to improve the yield.
Particularly, the so-called intrinsic gettering (hereinafter called IG) is generally well employed as a method of clean gettering, said IG using as a gettering site the bulk micro defects which generate in the wafer in the heat treatment process, being caused by the supersaturated oxygen involved in a CZ silicon single crystal. The IG capability is closely concerned with the BMD density, and the different kinds of elements require their respective IG capabilities correspondingly. In short, depending on the kind of devices the optimum BMD density for the wafer is required.
On the other hand, the initial Oi of a CZ silicon single crystal wafer commonly used is in the range 12.times.10.sup.17 to 18.times.10.sup.17 atoms/cc, and to obtain the optimum BMD density a preheat treatment is carried out for the production of an oxygen precipitate nucleus at 600.degree.-900.degree. C. depending on the initial Oi of the wafers of the respective substrates.
In the wafer which can be internally generated with the BMD density determined by the gettering capability by the heat treatment in the manufacturing process of the semiconductor devices, a thermal stress often occurs due to the temperature gradient within the wafer face, following the insertion into and drawing from the heat treatment furnace, when a displacement and propagation takes place in the wafer by the bulk micro defects thereby deforming the wafer not a little whereby a SORI or a slip of continuous defects generates. The portion thus slipped deteriorates the characteristics of the devices. On the other hand, even the SORI of a wafer brings about a pattern slip in the fine processing such as mask mating. Thus both the SORI and slipping lower the device yield.
SUBJECT MATTER OF THE INVENTION
The present invention has been made to solve the above problems, and it is characterized in that when the limit value of the SORI of the wafer after passing the device process, and the BMD density, are specified in predetermined ranges for a silicon single crystal to be a device, being required by the device yield and the gettering capability in making a semiconductor device, said wafer having the initial Oi sufficient to simultaneously satisfy said predetermined ranges, is subjected to a preheat treatment by using a time that can simultaneously satisfy a predetermined range between the upper limit and lower limit values of said initial Oi and the predetermined range of said BMD density.
In other words, there is previously obtained, for each group of silicon wafers in plurality having different initial oxygen concentrations, a relation between the BMD density within the wafers in the heat treatment in said device making process or the simulation heat treatment, and the SORI of the wafers. Then, there are obtained based on said relation the upper limit value (x) and lower limit value (y) of the initial Oi, which intersect in the region that simultaneously satisfy the limit value (a) of the SORI and the BMD density range (b), said upper and lower limit values (x) and (y) being determined when said limit value (a) and said density range (b) are specified, being restricted by the device yield and the gettering capability. On the other hand,
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Proceedings of the 12th Conference on Solid State Devices, Tokyo, 1980; Japanese Journal of Applied Physical, vol. 20 (1981), Supplement 20-1, pp. 25-30.
Applied Physics, vol. 49, No. 1 (1980), pp. 90-96.
Kawahara Hiroyuki
Kono Mitsuo
Fourson George
Komatsu Electronic Metals Co. Ltd.
Mulpuri S.
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