Process for positioning an interconnection line on an electric c

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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29591, 156644, 156646, 156651, 156656, 1566591, 204192E, 357 65, 427 88, 430313, 430318, C23F 102, B44C 122, C03C 1500, C03C 2506

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045444455

ABSTRACT:
The invention relates to a process for the positioning of an interconnection line on an electric contact hole in an integrated circuit. According to the invention, one or more conductive layers forming a conductive covering are deposited on the complete integrated circuit. The first conductive layer is deposited by an isotropic process. The interconnection line to be produced is then masked by a resin layer, followed by the successive etching of each conductive layer. Finally, an overetching of these conductive layers is effected in the electric contact hole, followed by the elimination of the resin.

REFERENCES:
patent: 4062720 (1977-12-01), Alcorn et al.
patent: 4076860 (1978-02-01), Kuroda
patent: 4307179 (1981-12-01), Chang et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980, Chromium as an RIE Etch Barrier, Hitchner et al., pp. 4516-4517.

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