Process for plasma etching polysilicon to produce rounded profil

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156643, 156646, 156657, 1566591, 156662, 437233, 437249, 437981, H01L 21308

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047189738

ABSTRACT:
In a silicon integrated circuit manufacturing process a layer of polysilicon is ion implanted with an n-type dopant and etched through a mask with a fluorine:chlorine mixture. The etchant undercuts at the mask to an extent dependent on the ratio of chlorine:fluorine and on the dopant level. By appropriately selecting that ratio and dopant level, polysilicon islands having a rounded profile can be achieved, this being most efficacious for subsequent deposition onto the polysilicon.

REFERENCES:
patent: 3892606 (1975-07-01), Chappelow et al.
patent: 4473435 (1984-09-01), Zafiropoulo et al.
patent: 4554728 (1985-11-01), Shepard
Adler, "Combined Shallow and Deep Junction Self-Aligned MOSFET Process", IBM TDB, vol. 24, No. 8, Jan. 1982, pp. 4186-4187.

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