Process for planarization and recess etching of integrated...

Details Process for planarization and recess etching of integrated... Process for planarization and recess etching of integrated...

2002-08-16

2003-07-15

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S706000, C438S710000, C438S719000, C438S657000

Reexamination Certificate

active

06593242

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
For a number of uses, e.g. for fabricating capacitors within integrated circuits, cavities are created in the lower layer of the circuit. Such cavities are generally called trenches. When forming a capacitor, such a cavity is also called a deep trench.
Conventionally, a trench is formed in the single crystal silicon and is then later filled with polysilicon. The polysilicon is deposited onto the entire surface of the wafer containing the integrated circuit and into the trench. This is done, for example with a low pressure chemical vapour deposition process. The deposition leads to a layer that completely fills the trench. To ensure that the trench is completely filled, the trench is overfilled which leads to a polysilicon layer with minor indentations that indicate the location of the trenches.
After the deposition of the polysilicon, the excessive polysilicon must be removed. This is conventionally done by two process steps which are called Planarization and Recess etch. In the first step, a CMP (chemical mechanical polishing) process is utilised to remove any polysilicon from the uppermost surface. So that the structure of the silicon is not impaired, a nitride layer is deposited onto the silicon prior to forming the trench. This nitride layer acts as an etch and polish stop layer. The CMP planarization is processed with a fixed time. This provides the opportunity to overpolish the polysilicon. Next, the recess etch step, a plasma etch process, is used to remove some of the polysilicon from within the trenches.
This known process has a severe disadvantage. While all other polysilicon planarizations employed in manufacturing integrated circuits can be done within integrated processes, the CMP process of this planarization has to be handled separately. This complicates the planarization, increases the risk of damage, and results in a higher cost.
U.S. Pat. No. 5,252,506 discloses a method for etching a trench filled with polysilicon. The polysilicon top layer is first etched with SF6/He in a timed etch process. The resulting structure is followed by patterning the polysilicon top layer to create openings. An additional patterning step occurs by coating, exposing, and developing a resist. Finally, a two step poly overetch follows using SF6/He in the first step and Cl1/He in the second step.
In the article Shrinath Ramaswami et al.: “Polysilicon Planarization Using Spin-On Glass”, Journal of the Electrochemical Society, Vol. 139, No. 2, Feb. 1, 1992, pages 591-599 a trench filled with polysilicon is first coated with spin-on glass using carbone/fluorine etch chemistry with changing C/F-ratios.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit which overcomes the above-mentioned disadvantages of the prior art processes of this general type.
In particular, it is an object of the present invention to modify the planarization step and the recess etch step in order to arrive at a process that can be better integrated.
With the foregoing and other objects in view there is provided, in accordance with the invention, a process for forming a recess in at least one polysilicon overfilled trench in an integrated circuit. The process includes steps of: uniformly etching a polysilicon overfill layer using a gas mixture including SF6 and CF4; stopping the etching before the polysilicon layer is completely removed from a surface of the integrated circuit; and recess etching the polysilicon layer with microtrenching properties using a gas mixture including hydrogen bromine and chlorine for forming a substantially planar surface of the polysilicon layer within the trench.
In accordance with an added feature of the invention, the etching includes a plasma etching.
In accordance with an additional feature of the invention, the stopping of the etching is decided based on measuring a layer thickness of the polysilicon layer.
In accordance with another feature of the invention, the measuring of the layer thickness of the polysilicon layer is performed by interference spectrometry.
In accordance with a further feature of the invention, a nitride layer is interposed between the silicon of the integrated circuit and the polysilicon layer.
In accordance with a further added feature of the invention, the interference spectrometry uses the polysilicon layer and the nitride layer.
In accordance with a further added feature of the invention, the stopping of the etching is performed when the polysilicon layer that remains is between 10 and 30 nm thick.
In accordance with a further additional feature of the invention, the stopping of the etching is performed when the polysilicon layer that remains is about 20 nm thick
In accordance with yet an added feature of the invention, the recess etching is performed using a helium/oxygen mixture.
In accordance with yet an additional feature of the invention, the trench is part of a capacitor.
In accordance with yet another feature of the invention, the polysilicon layer is deposited onto the integrated circuit using a low-pressure chemical vapour deposition process.
In accordance with an added feature of the invention, the etching of the polysilicon layer and the recess etching of the polysilicon layer are performed within the same etch chamber, preferably without breaking the vacuum.
By using the inventive process, the CMP process step which was hitherto necessary, can be entirely avoided. The inventive process allows an integrated approach, so that an interruption is no longer needed.
The etching step may include a plasma etching. In general, this step will be performed as any plasma etching commonly known to be suitable for etching polysilicon layers, e.g. with a high density plasma etch tool, i.e. a particular kind of plasma chamber.
The time to stop the etching is preferably determined based on measuring the layer thickness of the polysilicon layer. By monitoring the thickness of the remaining polysilicon layer, the inventive process can be fine tuned to achieve the desired aim.
Such measuring of the thickness of the polysilicon layer can be performed by interference spectrometry, which allows a precise measurement of the thickness. The interference spectroscopy uses the reflection of the emitted waves from surfaces. Throughout the etching process, when the thickness of the polysilicon layer decreases below a certain threshold, the layer becomes transparent for the incident light which is then also partly reflected from the next surface, e.g. the base silicon or a further layer overlaying this silicon.
Such a further layer may be a nitride layer that is interposed between the silicon of the integrated circuit and the polysilicon layer. Depositing such a layer on the surface of the silicon is in fact a routine measure in order to protect the silicon from undesired degradation throughout the manufacturing steps of integrated circuits.
Accordingly, the interference spectrometry may use the polysilicon layer and the nitride layer as the two reflective surfaces required for interference spectroscopy.
The thickness of the polysilicon layer that should remain on the surface depends on the particular geometric conditions of the trench and on the thickness of the polysilicon layer that is intended to be on the bottom of the trench. In many typical applications, like forming capacitors, the etching will be stopped when the remaining polysilicon layer is between 10 and 30 nm thick.
The etching can, for example, be stopped when the remaining polysilicon layer is about 20 nm thick. This value has been proven to be useful in the manufacturing of capacitors in DRAM structures.
The thickness of the layer correlates with the values determined by interference spectroscopy. The correlation does not need to be calculated, but may be determined experimentally. For this purpose, the etching of samples is stopped, their values for spectrometry is determined, and a cross section of same is subjected to elec

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