Process for planarization a semiconductor substrate

Details Process for planarization a semiconductor substrate Process for planarization a semiconductor substrate

2000-07-27

2002-05-21

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S481000

Reexamination Certificate

active

06391798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention is related to device processing and in particular to a process for planarizing the surface of a semiconductor substrate on which devices are subsequently formed.
2. Art Background
In semiconductor device fabrication, the devices (e.g. integrated circuits) are formed on semiconductor substrates that are typically referred to as wafers. The wafers themselves are formed by slicing a cylindrical ingot of semiconductor (e.g. silicon) material. The ingot is sliced with a saw. The resulting wafers sawed from the ingot have a rough surface.
Typically, the wafers sawed from the ingot are polished (referred to as lapping) to smooth the surface and provide the surface with a planar geometry that is suitable for subsequent device fabrication. In a conventional lapping process, a slurry of abrasive particles (e.g., Al
2
O
3
) is used to smooth the surface of the wafer. The lapped surface is then etched in an isotropic etchant (e.g. KOH) to remove surface damage and debris.
However, as noted in U.S. Pat. No. 4,874,463 to Koze et al., even after lapping and etching, pits or depressions remain in the wafer surface. Koze et al. proposes an alternative method for wafer polishing. In the Koze et al. method, an etch resistant coating is formed on the wafer surface. The etch resistant coating is removed from the high points on the horizontal surface of the wafer. An isotropic etching process is used to remove the wafer surface down to the depths of the pit. The isotropic etchant undercuts the protective coating. But, because only the high points of the wafer surface are exposed to the etchant initially, the high points are removed. After the isotropic etch, the remaining portions of the protective coating are removed. The wafer is then polished to remove any remaining protrusions. Koze et al. contemplate that both major surfaces may be polished in this manner.
Although processes such as the one described in Koze et al. provide wafer surfaces that are adequently smooth, such processes are complex and time-consuming. Accordingly, wafer smoothing processes that are comparatively simple and less time-consuming, yet provide suitable smooth wafer surfaces, are sought.
SUMMARY OF THE INVENTION
The present invention is a process for planarizing the major surfaces of a semiconductor substrate after the semiconductor substrate has been sawed from a semiconductor ingot. The initial topography of the substrate surface results from sawing the wafer from the ingot and any subsequent lapping. The process of the present invention uses an object with a flat surface to planarize a material of appropriate viscosity after it is formed on the substrate surface. That is, the planarization material is forced into planarity by contacting the planarization material with the object having a flat surface.
Objects with sufficiently flat surfaces for use in the present invention are well known to one skilled in the art. One example of such an object is an optical flat made of fused silica. The flat surface is configured to transfer the desired degree of planarity to the planarization material.
The planarization material should have a viscosity of about 20 centipoise to about 1000 centipoise, preferably about 60 centipoise to about 200 centipoise and most preferably about 100 centipoise, (after it is applied to the substrate surface and the solvent is evaporated). The viscosity is controlled by controlling the temperature (i.e. the higher the temperature, the lower the viscosity and vice-versa). However, the temperature of the wafer is maintained within conventional process limits. This viscosity is referred to herein as the preplanarization viscosity to distinguish it from the viscosity of the planarization material at other points in the process. The planarization material is solidified (i.e. hardened) while in contact with the flat surface by curing or by some other mechanism for solidifying the planarization material. The curing conditions depend upon the particular planarization material. Upon solidification e.g., curing, the volume of the planarization material is reduced by less than about 10%. The cured planarization material has a surface planarity such that the variations in height over any 3 cm by 3 cm area of the planarization material do not exceed about 300 nm. A surface planarity with height various (over a given 3 cm×3 cm area) of 100 nm or less is obtainable using the process of the present invention. In fact, the inventive process can provide a surface planarity with height variations of less than 50 nm if required.
After the planarization material is cured, or after its viscosity has been increased, the flat surface is separated from contact with the planarization material. It is advantageous if a release agent is on the flat surface prior to planarization in order to facilitate this separation without degrading the planarity of the planarization material. The composition of the release agent will depend upon the composition of the planarization material. For example, if the planarization material is an epoxy material, the release agent on the flat surface is a material that is inert with respect to the epoxy material. That is, there is substantially no adhesive force between the release agent and the epoxy material when the flat surface is separated from contact with the epoxy material.
The present invention contemplates that at least one substrate surface is planarized in the above-described manner. In an additional embodiment both major surfaces are planarized simultaneously. In this embodiment, it is advantageous if the major surfaces are lapped after sawing but before planarization. The lapping step provides two major surfaces that are approximately parallel.
Both major surfaces are planarized simultaneously by using two objects with sufficiently flat surfaces. The process of simultaneous planarization is illustrated schematically in
FIGS. 1 and 2
. The substrate
10
with the layer of planarization material
15
formed on both major surfaces
11
is placed between the two objects
20
. Referring to
FIG. 2
, the two objects
20
are then placed in contact with the substrate
10
having the planarization material
15
formed on both major surfaces
11
.
Once the planarization material is planarized and hardened, the planar surface is then transferred into the major surface of the substrate. In the embodiment of the present invention where both surfaces are planarized, this step is done separately for each surface. The planar surface is transferred into the underlying substrate using known processing techniques such as plasma reactive ion etching. It is advantageous if the planarization material has an etching resistance that is about the same as the etch resistance of the underlying semiconductor substrate. Suitable etching conditions to effect the desired transfer will depend upon the particular materials that are to be etched. Such etching conditions are known to those skilled in the art. Typically, the semiconductor substrate is a silicon wafer or a wafer made of a III-V material (e.g. silicon germanium) wafer.


REFERENCES:
patent: 4874463 (1989-10-01), Koze et al.
patent: 6048799 (2000-04-01), Prybyla

Affiliated with

Also associated with

Rating

Process for planarization a semiconductor substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for planarization a semiconductor substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for planarization a semiconductor substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2875140