Process for obtaining a transistor having a silicon-germanium ga

Details Process for obtaining a transistor having a silicon-germanium ga Process for obtaining a transistor having a silicon-germanium ga

1998-06-23

1999-12-07

Chaudhuri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

257407, 438233, H01L 29772

Patent

active

059982896

ABSTRACT:
The process includes the deposition of a stack of Si/Si.sub.1-x Ge.sub.x /Si layers (2, 3, 4) on a gate oxide layer (1) in a single-wafer reactor and then the etching of the gate (GR) using an inorganic mask (5). Next, the gate (GR) is encapsulated in a material (7) which is non-oxidizing with respect to germanium before the isolating spacers (8) are formed.

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XP000481715 Kistler, et al., "Symmetric CMOS In Fully-Depleted Silicon-On-Insulator Using P+ -Polycrystalline Si-Ge Gate Electrodes,"IEDM, published Dec. 5, 1993, pp. 30.2.1 through 30.2.3.
Search Report for FR 9707938 dated Mar. 12, 1998.

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