Process for minimizing encroachment effect of field isolation st

Details Process for minimizing encroachment effect of field isolation st Process for minimizing encroachment effect of field isolation st

1996-08-19

1997-05-27

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438449, 438451, H01L 2176

Patent

active

056331916

ABSTRACT:
A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a polysilicon layer is deposited on a laminate comprising a substrate having thereon a pad oxide, and the stacked layers on the pad oxide. An overhang layer is deposited on the polysilicon layer, and a photo-resist mask which masks the active regions is then applied so as to remove the unmasked overhang layer and the unmasked polysilicon layer. The resultant structure is isotropically etched to partially undercut the vertical portions of the polysilicon layer under the overhang layer so as to form an overhang. The photo-resist is stripped, and the stacked layers not covered by the overhang layer are etched anisotropically. The channel-stop ions are implanted, and the overhang layer is removed. Anisotropically etch the stacked layers by using the polysilicon layer as a mask, and then the resultant structure is subjected to oxidation to form the isolation regions. The channel stop region is self-aligned to the resultant field oxide and the isolation structure is free of the impurity encroachment effect.

REFERENCES:
patent: 4755477 (1988-07-01), Chao
patent: 5104829 (1992-04-01), Shida
patent: 5208181 (1993-05-01), Chi
patent: 5358893 (1994-10-01), Yang et al.
patent: 5397733 (1995-03-01), Jang

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