Process for metallic contamination reduction in silicon wafers

Details Process for metallic contamination reduction in silicon wafers Process for metallic contamination reduction in silicon wafers

2006-08-01

2006-08-01

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Gettering of substrate

By layers which are coated, contacted, or diffused

C438S058000, C438S143000, C438S210000, C438S402000

Reexamination Certificate

active

07084048

ABSTRACT:
A process for removing a contaminant selected from among copper, nickel, and a combination thereof from a silicon wafer having a surface and an interior. The process comprises cooling the silicon wafer in a controlled atmosphere from a temperature at or above an oxidation initiation temperature and initiating a flow of an oxygen-containing atmosphere at said oxidation initiation temperature to create an oxidizing ambient around the silicon wafer surface to form an oxide layer on the silicon wafer surface and a strain layer at an interface between the oxide layer and the silicon wafer interior. The cooling of the wafer is also controlled to permit diffusion of atoms of the contaminant from the silicon wafer interior to the strain layer. Then the silicon wafer is then cleaned to remove the oxide layer and the strain layer, thereby removing said contaminant having diffused to the strain layer.

REFERENCES:
patent: 6100167 (2000-08-01), Falster et al.
patent: 6194327 (2001-02-01), Gonzalez et al.
patent: 6562733 (2003-05-01), Horikawa
patent: 2003/0104680 (2003-06-01), Stefanescu et al.
patent: 3939661 (1991-06-01), None
patent: 60055629 (1985-03-01), None
patent: 63129633 (1988-06-01), None
Ghandhi, Sorab K., VLSI Fabrication Principles, Silicon and Gallium Arsenide, 1983 by John Wiley and Sons, pp. 517-519.
Abe, A History and Future of Silicon Crystal Growth, Electrochem. Soc. Proceed., vol. 98-1, pp. 157-178, 1998.
Adachi, et al., Reduction of Growth-In Defects by High Temperature Annealing, J. Electrochem. Soc., vol. 147, No. 1, pp. 350-353, 2000.
Graf, et al., Improvement of Czochralski Silicon Wafers by High-Temperature Annealing, J. Electrochem. Soc., vol. 142, No. 9, pp. 3189-3192, 1995.
Graf, et al., Characterization of Crystal Quality by Crystal Originated Particle Delineation and the Impact on the Silcon Wafer Surface, J. Electrochem. Soc., vol. 145, No. 1, pp. 275-283, 1998.
Iida, et al., Effects of Light Element Impurities on the Formation of Grown-In Defects Free Region of Czochralski Silcon Single Crystal, Electrochem. Soc. Proceed., vol. 99-1, pp. 499-510, 1999.
Ingle & Crouch, Spectrochemical Analysis, Prentice Hall, pp. 577-590, 1988.
Neumann, et al., Ultra-Trace Analysis of Metallic Contaminations on Silicon Wafer Surfaces by Vapour Phase Decomposition/Total Reflection X-Ray Fluoresence, Spectrochimica Acta, vol. 46B, No. 10, pp. 1369-1377, 1991.
Shimura, Semiconductor Silicon Crystal Technology, Academic Press, Inc. pp. 188-191 & Appendix XII, 1989.
Silicon Chemical Etching, J. Grabmaier, Springer-Verlag, New York, pp. 3-19, 1982.
Tamatsuka, et al., Oxide Defect Annihilation/Generation Following High Temperature Annealing: A Gate Oxide Integrity Evaluation, Electrochem. Soc. Proceed., vol. 97-3, pp. 183-194, 1997.
Verhaverbeke, et al., The Effect of H2Annealing on the SI Surface and its Use in the Study of Roughening During Wet Chemical Cleaning, Electrochem. Soc. Proceed., vol. 93-8, pp. 1170-1181, 1993.
Vanhellemont, et al., On the Nature of Grown-In Defects in Silicon: Dependence on Pulling Conditions and Evolution During Thermal Treatments, Electrochem. Soc. Proceed., vol. 96-13, pp. 226-237.
Tamatsuka, et al., High Performance Silicon Wafer with Wide Grown-In Void Free Zone and High Density Internal Gettering Site Achieved Via Rapid Crystal Growth with Nitrogen Doping and High Temperature Hydrogen and/or Argon Annealing, Electrochemical Society Proceedings, May 1999, vol. 99, No. 1, pp. 456-467.
Bai, et al., Intrinsic Cu Gettering at a Thermally Grown SiO2/Si Interface, J. Appln. Phys., vol. 68, No. 7 Oct. 1990, pp. 3313-3316.
Hozawa, et al., Copper Distribution Near a Si02/Si Interface Under Low-Temperature Annealing, Japanese J. Appl. Phys., vol. 41, No. 10, Oct. 2002, pp. 5887-5893.

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