Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-04-17
2002-12-24
Baxter, Janet (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S314000, C430S317000, C430S328000, C430S330000, C216S041000, C438S710000, C438S713000
Reexamination Certificate
active
06497992
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for manufacturing a semiconductor integrated circuit device having a ferroelectric (high relative dielectric constant substance) capacitor and, more particularly, to a technique which is effective when applied to a process for manufacturing a ferroelectric (high relative dielectric constant substance) capacitor by using a conductive material for producing reaction products of low vapor pressure at a dry-etching time.
In order to compensate the reduction in the amount of stored charge with the miniaturization of the memory cell of a large capacity DRAM (Dynamic Random Access Memory) exceeding 256 Mbits or 1 Gbits, it is demanded that the capacitor insulating film of a data storing capacitive element (or capacitor) is made of a high relative dielectric material having a specific relative dielectric constant of 20 or more such as Ta
2
O
5
or BST ((Ba,Sr)TiO
3
), or a ferroelectric material having a relative dielectric constant over 100 such as PZT (PbZr
x
Ti
1−x
O
3
), PLT (PbLa
x
Ti
1−x
O
3
), PLZT, PbTiO
3
, SrTiO
3
or BaTiO
3
.
In the field of a nonvolatile memory, there has been developed a ferroelectric memory which utilizes the polarization inversion of the ferroelectric material for data storage.
When the capacitor insulating film of the capacitor is made of an aforementioned ferroelectric substance (high relative dielectric constant substance), it is necessary to make the conductive films for electrodes sandwiching the capacitor insulating film, of such a refractory metallic material, e.g., Pt having a high affinity with those materials.
When the capacitor is made of Pt or PZT, there arises the following problem. When the thin film of Pt or PZT deposited on the substrate is dry-etched, it is known that a lot of reaction products having a low vapor pressure are deposited on the side face of a pattern to cause the short-circuiting between the capacitors.
In order to prevent reaction products from being deposited on the side face of the pattern when the Pt film is to be dry-etched, there is known in the prior art either a method of tapering the side face of a photoresist used as the etching mask or a method of using a hard mask of a silicon oxide film or a metal film in place of the photoresist.
It has been reported in 27p-N-9, Preprint No. 2 of the 43rd Joint Congress of Applied Physics of Japan 1996, that a clean capacitor without any side wall deposited film can be formed by using a resist mask having a side face tapered at about 75 degrees when a three-layered film of Pt/PZT/Pt deposited on a substrate is dry-etched. This can be thought in the following manner. If the side face of the resist mask is tapered, the side face of the pattern is also irradiated with etching ions so that the etch-off rate is enabled to exceed the deposition rate of the side wall deposited film by increasing the taper angle over a predetermined value (e.g., about 75 degrees).
It has been reported in 26a-ZT-4, Preprint No. 2 of 56th Joint Congress of Applied Physics of Japan 1995, that the Pt film can be tapered to effect the etching without any side wall deposited film, when the Pt film is dry-etched, by using as the mask a silicon oxide film etched to a predetermined pattern and by using an etching gas containing Ar and additional oxygen.
Japanese Patent Laid-Open No. 89662/1993 has disclosed a method of forming an excellent Pt pattern having no side wall deposited film by using as the mask a Ti film etched to a predetermined pattern thereby to etch the Pt film.
The RIE etching technique using a tapered resist mask has been disclosed on pp. 244 to 253, “Glow Discharge Processes SPUTTERING AND PLASMA ETCHING”, by Brian Chapman.
SUMMARY OF THE INVENTION
According to our investigations, however, the prior art method of patterning the Pt film by using the resist mask having the tapered side face has problems of not only a complicated step of tapering the side face of the resist mask but also a difficulty in forming a fine Pt pattern in a high sizing accuracy.
On the other hand, the method of using the hard mask of the silicon oxide film or the metallic film forms a hard mask pattern by dry-etching such a film deposited on the Pt film, and has a problem of an increase in the steps, compared to the case of using the resist mask. During the etching, moreover, the hard mask has to be heated to as high as 300° C. to raise other problems that when the Pt film over the ferroelectric (high relative dielectric constant substance) film is etched, the underlying ferroelectric (high relative dielectric constant substance) film is deteriorated, and that the hard mask is difficult to ash off after the end of the etching.
An object of the present invention is to provide a technique which can form a fine pattern, when a thin film of Pt or the like deposited on a substrate is patterned by a dry-etching method using a resist mask, without leaving reaction products of low vapor pressure on the side face of the pattern and in a high dimensional accuracy.
The aforementioned and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
The summaries of the invention will be briefly described in the following.
(1) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising the step of patterning by a dry-etching method a thin film, which has one or a plurality of films including a film formed directly or indirectly over a first major surface of a wafer and liable to be deposited on a side wall, by using as the mask a photoresist film of a predetermined pattern, which has a generally vertical side face of at least its lower half and which is either normally tapered or rounded at the outer periphery of its head, so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof.
(2) The thin film pattern is overetched, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(3) The thin film includes a platinum thin film.
(4) The thin film includes a high relative dielectric constant thin film or a ferroelectric thin film.
(5) According to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising:
(a) the step of forming a thin film, which has one or a plurality of films including a film liable to be deposited on a side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a photoresist of a predetermined pattern, which has a generally vertical side face of at least its lower half and which is either normally tapered or rounded at the outer periphery of its head, directly or indirectly over the thin film; and
(c) the step of patterning by a dry-etching method the thin film by using as the mask the photoresist film of the predetermined pattern so that the side face of the thin film pattern may be normally tapered so as to reach the lower end thereof.
(6) The thin film pattern is overetched, after having been formed, to remove the side wall deposited film which is left on the side face of the thin film pattern.
(7) The thin film includes a platinum thin film.
(8) The thin film includes a high relative dielectric constant thin film or a ferroelectric thin film.
(9) According to the present invention, there is provided a semiconductor integrated circuit device manufacturing process, comprising:
(a) the step of forming a thin film, which has one or a plurality of films including a film liable to be deposited on a side wall, directly or indirectly over a first major surface of a wafer;
(b) the step of forming a positive type benzophenone novolak resist film by spin-coating over the thin film;
(c) the step of forming a predetermined resist film pattern by exposing and developing the positive type benzophenone novolak resist film;
(d) the step of setting the r
Abe Jun
Kumihashi Takao
Murai Fumio
Sasabe Shunji
Suko Kazuyuki
Antonelli Terry Stout & Kraus LLP
Baxter Janet
Walke Amanda C.
LandOfFree
Process for manufacturing semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacturing semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing semiconductor integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2969287