Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-08-24
2001-05-22
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S622000, C438S624000, C438S634000, C438S672000
Reexamination Certificate
active
06235620
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for manufacturing a semiconductor integrated circuit device and, more particularly, to a technique for exposing semiconductor regions over the surface of a semiconductor substrate in self-alignment to wiring lines (including gate electrodes) and element isolating regions when connection holes are to be formed in a flattened layer insulating film.
As a first technique, the SAC (Self-Aligned Contact) technique for forming connection holes in a layer insulating film covering gate electrodes and in self-alignment with the gate electrodes is described on pp. 1864 to 1869 of IEEE Transaction ED-43, No. 11 (1996), for example. Here is disclosed a technique in which the gate electrodes are constructed to have the so-called “poly-metal structure”, which means that a refractory metal film is laminated over a low-resistance poly-silicon film through a barrier metal film, and a cap insulating film over the gate electrodes and a side wall insulating film on the sides of the gate electrodes are formed of a silicon nitride film.
According to this technique, when the connection holes are to be formed in the layer insulating film of a silicon oxide film, they can be formed in self-alignment with the gate electrodes by etching them selectively with respect to the silicon nitride film. This makes it unnecessary to take a margin between the gate electrodes and the connection holes so that the size of a MISFET can be reduced to increase the number of MISFETs to be packaged in a chip of a predetermined size thereby to raise the degree of integration.
Here, as seen from the aforementioned first technique, the main flow is the element isolation structure (as called the “trench isolation”) in which the element isolating insulating film made of a thermally oxidized film is replaced by the trenches formed in the surface of the semiconductor substrate and buried with a CVD oxide film or the like.
In the case of the aforementioned first technique, a margin has to be so retained between the opening of a photoresist mask and the element isolating regions that the opening of the mask does not extend over the element isolating regions when the connection holes are to be formed. If the opening of the photoresist mask extend over the element isolating regions, the oxide film in the trenches will also be etched at the time of etching the layer insulating film thereby to cause a danger of conduction between the semiconductor regions and the substrate.
Thus, it is needless to say that the retention of the margin between the mask opening and the element isolating regions raises a cause for preventing the size reduction of the MISFETs.
Although not well known in the art, on the other hand, here will be described a second technique (Japanese Patent Application No. 92608/1997) for forming the connection holes in self-alignment with the gate electrodes but without any margin from the element isolating regions.
In this second technique, a cap insulating film formed of only a silicon nitride film is formed over the gate electrodes, and the principal face of a semiconductor substrate, the side faces of the gate electrodes and the surface (including the side faces and the upper face) of the cap insulating film are coated with a thin silicon nitride film. In this second technique, the aforementioned connection holes for exposing the semiconductor substrate are formed at first by performing an etching treatment under such a condition that a layer insulating film made of a silicon oxide film is more easily etched off than the silicon nitride film, and when the thin silicon nitride film is exposed, by performing an etching treatment under such a condition that the silicon nitride film is more easily etched off than the layer insulating film. According to this second technique, it is possible to solve the problem that even if a silicon oxide film of the same kind as that of the layer insulating film is buried in the element isolating regions formed in the semiconductor substrate, the silicon oxide film buried in the element isolating regions is etched to establish the conduction between the semiconductor regions and the substrate at the time of forming connection holes.
SUMMARY OF THE INVENTION
The invention relates to a further improvement of the aforementioned second technique, and we have found out that the aforementioned second technique has the following problems.
The first problem is an increase in the aspect ratio of the aforementioned connection holes. According to the second technique, at the time of forming the aforementioned connection holes, the thin silicon nitride film over the semiconductor substrate is finally etched to expose the surface of the semiconductor substrate. According to the aforementioned technique, however, the cap insulating film is also formed of the silicon nitride film so that the cap insulating film portion, as exposed from the connection holes, is also etched off. When the cap insulating film is removed, however, the insulating film between the conductive film to be buried in the connection holes and the gate electrodes is thinned to lower the breakdown voltage. When the cap insulating film is completely etched to expose the gate electrodes, on the other hand, the conduction is established between the conductive film buried in the connection holes and the gate electrodes. It is, therefore, necessary to thicken the cap insulating film to such an extent that the cap insulating film may be formed over the gate electrodes after the formation of the connection holes was ended. With the cap insulating film being thickened, the height from the principal face of the semiconductor substrate to the upper face of the cap insulating film becomes larger than the ordinary one so that the aspect ratio of the connection holes increases. This makes it difficult to form the connection holes and to bury the conductive film in the connection holes, thereby to cause an increase in the electric resistance and a defective conduction in the connection holes.
The second problem is that the cap insulating film is scraped or bulged by a heat treatment after the cap insulating film was worked. In the aforementioned second technique, it is necessary to retain the thickness of the cap insulating film. According to our investigation results, however, it has been found out that as the cap insulating film becomes the thicker, the problem of the separation or expansion of the cap insulating film is made the more serious by the heat treatment after the formation of the cap insulating film. According to our investigation results, on the other hand, it has also been found out that the problem is serious when the gate electrode material (especially, the material at the portion where the cap insulating film contacts) is a refractory metal film.
On the basis of the invention, on the other hand, we have searched examples of the prior art on the SAC technique and have found out Japanese Patent Laid-Open No. 316313/1996 and Japanese Patent Laid-Open No. 125141/1996.
In
FIG. 1
of the publication of the first searched technique, there is shown a process in which: an offset insulating film of silicon oxide is formed over gate electrodes; a silicon nitride film is then deposited and etched back; a side wall of a silicon nitride film is formed on the side walls of the gate electrodes; a thin silicon nitride film and a layer insulating film are deposited all over; the layer insulating film is etched under such a condition that a high etching selection ratio is set for the thin silicon nitride film and the side wall; and the thin silicon nitride film in the bottoms of contact holes is then etched to expose the substrate.
Since the etching selection ratio between the silicon oxide film and the silicon nitride film cannot be made infinite, according to this first searched technique, the thin silicon nitride film over the gate electrodes is etched, too, while the layer insulating film between the gate electrodes is being etched. This makes it necessary for this thin silic
Kawakami Hiroshi
Saito Masayoshi
Umezawa Tadashi
Yoshida Makoto
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Quach T. N.
LandOfFree
Process for manufacturing semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacturing semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing semiconductor integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2565248