Process for manufacturing semiconductor device

Details Process for manufacturing semiconductor device Process for manufacturing semiconductor device

2006-04-04

2006-04-04

Dildine, R. Stephen (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S723000

Reexamination Certificate

active

07024604

ABSTRACT:
A semiconductor device manufacturing process which includes a test process that minimizes the test time for a single wafer, reduces the test cost and improves the throughput. The test system is made up of a wafer which includes plural chips formed with flash memories, a wafer level whole-surface contact device for contact with the whole surface of the wafer, a tester for testing electric characteristics of the wafer, and a BOST board interposed between the tester and the wafer level whole-surface contact device and with chip-by-chip control circuits mounted thereon. Where the test time differs depending on each chip in the wafer, the BOST board controls each test item for each chip so that in a parallel manner for the chips, upon completion of a preceding test, a shift is made to the next test.

REFERENCES:
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 6591385 (2003-07-01), Krech et al.
patent: 2002/0046374 (2002-04-01), Aoki et al.
patent: 2003/0038365 (2003-02-01), Farnworth et al.
patent: 06342600 (1994-12-01), None

Affiliated with

Also associated with

Rating

Process for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3540273