Process for manufacturing an offset gate structure thin film tra

Details Process for manufacturing an offset gate structure thin film tra Process for manufacturing an offset gate structure thin film tra

1995-05-05

1996-01-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 21, 437 44, 148DIG150, H01L 2186

Patent

active

054880050

ABSTRACT:
A process for manufacturing an offset gate structure thin film transistor which includes the steps of forming a first semiconductor layer, e.g., an active layer made of amorphous silicon or polysilicon, on a major surface of a substrate, e.g., a glass substrate of an LCD, forming a buffer layer on the first semiconductor layer, etching away a first region of the buffer layer and etching a corresponding region of the first semiconductor layer to a predetermined depth, to thereby form a recess and an underlying thin channel region in the first semiconductor layer, the thin channel region having a thickness less than that of the remainder of the first semiconductor layer, forming a second semiconductor layer on the buffer layer and exposed portions of the first semiconductor layer defining the recess, forming a gate insulating layer on the second semiconductor layer, forming a conductive layer on the gate insulating layer, etching the second semiconductor layer, the gate insulating layer, and the conductive layer so as to form a gate electrode structure overlying the thin channel region of the first semiconductor layer and offset resistance regions of the first semiconductor layer disposed on opposite sides of the thin channel region, and, ion-implanting impurities into the first semiconductor layer through exposed portions of the buffer layer disposed on opposite sides of the gate electrode structure, to thereby form source and drain regions on opposite sides of the offset resistance regions of the first semiconductor layer.

REFERENCES:
patent: 4597160 (1986-07-01), Ipri
patent: 5116771 (1992-05-01), Karulkar
patent: 5294555 (1994-03-01), Mano et al.

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