Process for manufacturing a stacked integrated circuit package

Details Process for manufacturing a stacked integrated circuit package Process for manufacturing a stacked integrated circuit package

1994-10-18

1996-12-24

Niebling, John

Fishing, trapping, and vermin destroying

437208, 437915, H01L 2158, H01L 2160, H01L 2170

Patent

active

055873413

ABSTRACT:
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

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patent: 3689684 (1972-09-01), Cox, Jr. et al.
patent: 4271426 (1981-06-01), Hargis
patent: 4398235 (1983-08-01), Lutz et al.
patent: 4696525 (1987-09-01), Coller et al.
patent: 4763188 (1988-08-01), Johnson
"Wrap Around C-Clip", IBM TDK; vol. 5 No. 11 4-63 p. 14 K. J. Roche.

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