Process for manufacturing a SOI wafer with buried oxide...

Details Process for manufacturing a SOI wafer with buried oxide... Process for manufacturing a SOI wafer with buried oxide...

2000-04-26

2002-03-26

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S405000, C438S407000, C438S413000, C438S528000

Reexamination Certificate

active

06362070

ABSTRACT:

TECHNICAL FIELD
The present invention regards an improved process for manufacturing a SOI wafer with buried oxide regions without cusps.
BACKGROUND OF THE INVENTION
As known, according to present designs in the microelectronics industry, the substrate of integrated devices is obtained from monocrystalline silicon wafers. In the last few years, as an alternative to just silicon wafers, composite wafers have been proposed, so-called SOI (Silicon-on-Insulator) wafers formed by two silicon layers, one of which is thinner than the other, separated by a silicon oxide layer.
A process for manufacturing SOI wafers is the subject of European Patent Application No. 98830007.5 filed on Jan. 13, 1998 in the name of STMicroelectronics, S.r.l. and is described hereinafter with reference to
FIGS. 1
to
8
.
According to this process, on a surface
3
of a substrate
2
a first silicon oxide layer is initially grown and has a thickness comprised between, for example, 20 and 60 nm. Then a first silicon nitride layer with a thickness comprised between 90 and 150 nm is deposited. Using a resist mask, the uncovered portions of the first oxide layer and the first nitride layer are etched, and the resist mask is then removed to obtain the intermediate structure of
FIG. 1
, where the wafer thus obtained is indicated, as a whole, by
1
, and the portions of the first oxide layer and of the first nitride layer remaining after dry etching are indicated by
4
and
5
, and define respective first protective regions
7
covering first portions
8
′ of the substrate
2
.
The first protective regions
7
form a hard mask, indicated as a whole by
9
, used for etching the substrate
2
at second portions
8
″ left uncovered by the mask
9
so as to form initial trenches
10
(FIG.
2
).
Subsequently, as shown in
FIG. 3
, the wafer
1
is oxidized, thus forming a second oxide layer
11
, having a thickness comprised between, for example, 20 and 60 nm, covering the walls and the bottom of the initial trenches
10
, and then a second silicon nitride layer
12
is deposited for a thickness comprised between 90 and 150 nm.
Next, the layers
12
and
11
are etched anisotropically in an unmasked way. Given the etching anisotropy, the horizontal portions of the second silicon nitride layer
12
and of the silicon oxide layer
11
on the bottom of the initial trenches
10
, as well as the portion of the second silicon nitride layer
12
on top of the portions
4
and
5
are removed to yield the intermediate structure of
FIG. 4
, wherein the regions
8
′ are still covered on top by the mask
9
and laterally (on the vertical walls of the initial trenches
10
) by oxide and nitride portions
11
′ and
12
′. Instead, the substrate
2
is bare on the bottom
15
of the initial trenches
10
.
Then the uncovered silicon at the bottom
15
of the initial trenches
10
are etched to deepen the initial trenches
10
until final trenches
16
are obtained having a desired depth. In particular, the depth of the final trenches
16
determines the dimensions of the desired buried oxide layer, and hence the electrical characteristics of the SOI wafer, as clarified hereinafter, which is determined according to the requirements for the final SOI wafer.
The substrate
2
is now formed by a base portion indicated by
2
′ and by a number of “columns”
18
extending vertically from the base portion
2
′. The intermediate structure of
FIG. 5
is thus obtained, wherein the nitride portions
5
and
12
′ are no longer distinct from each another and are indicated by
19
; also the oxide portions
4
and
11
′ are no longer distinct from each another and are indicated by
20
, and form, together with the portions
19
, second protective regions
30
.
A thermal oxidation is then carried out, so that the exposed silicon regions of the “columns”
18
are converted into silicon oxide. In practice, a gradual growth of the oxide regions is obtained at the expense of the silicon regions, starting from the side walls of the final trenches
16
towards the inside of the columns, and in part also towards and inside the base portion
2
′. Since during oxidation the volume increases, the oxide regions being formed occupy, gradually, the space of the final trenches
16
until they completely close the trenches and join together. The oxidation ends automatically once the columns
18
have completely oxidized (apart from the top area or tip, indicated by
21
, which is protected by the second protective regions
30
) to form a continuous region of buried oxide
22
, illustrated in
FIG. 6
, wherein continuous vertical lines indicate the surfaces on which the oxide regions being formed meet starting from walls of two adjacent final trenches
16
, so as to highlight the oxide expansion.
Subsequently, by selective etching, the second protective regions
30
are removed so as to uncover the “tips”
21
, which form the nucleus for subsequent epitaxial growth.
The structure of
FIG. 7
, which shows the three-dimensional structure of the wafer
1
in this step, is obtained. Subsequently, epitaxial growth is performed, the parameters of which are chosen so as to prevent nucleation of the silicon in the areas overlying the buried oxide region
22
, and a high side growth/vertical growth ratio is chosen so as to obtain first a horizontal growth of the silicon around the tips
21
(and hence the coating of the top surface of the buried oxide region
22
), and subsequently the vertical growth of an epitaxial layer
23
. After a possible chemical and mechanical lapping to flatten the top surface of the wafer
1
, the final structure of wafer
1
shown in
FIG. 8
is thus obtained.
Thereby, it is possible to make a SOI wafer employing only processing steps that are commonly used in microelectronics, with costs that are much lower than those of the processes currently employed for making SOI substrates.
The above described manufacturing process presents, however, the drawback that the shape of the buried oxide region
22
is not ideal. In fact, as highlighted in the enlarged detail of
FIG. 9
, during thermal oxidation, the exposed silicon regions of the “columns”
18
are oxidized following the curved lines, so that the buried oxide region
22
presents, at the bottom, a shape defined by a series of arches
35
and, at the top, a shape defined by a series of cusps
37
extending upwards at each wall of the final trenches
16
. In addition, inside the buried oxide region
22
voids
38
are formed. This shape of the buried oxide region
22
thus renders the step of epitaxial growth of the silicon to form the SOI wafer critical, and, in any case, the shape of the bottom surface of the epitaxial layer
23
creates problems in forming suspended masses.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention is therefore to overcome the drawbacks of the above described manufacturing process. According to the present invention, a process for manufacturing SOI wafers is provided, including forming trenches in a wafer of monocrystalline semiconductor material, the trenches extending between and delimiting laterally protruding portions of the wafer; oxidizing at the bottom of the protruding portions and subsequently oxidizing the wafer underneath the trenches and underneath the bottom portions of the protruding portions to form at least one continuous buried oxide region overlaid by nucleus regions of the monocrystalline semiconductor material; and epitaxially growing a layer of crystalline semiconductor material starting from the nucleus regions.
In accordance with another aspect of the foregoing process, the forming of trenches includes forming masking regions that surround top portions of the protruding portions at the top and at the sides; forming retarding regions on the bottom of the trenches, with the masking regions and the retarding regions delimiting between each other oxidizable surfaces surrounding the bottom portions of the protruding portions.


REFERENCES:
patent: 4361600 (198

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