Process for manufacturing a silicon semiconductor device...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S783000, C148S033300

Reexamination Certificate

active

06340642

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention concerns a process for reducing the surface recombination velocity of silicon wafers.
When manufacturing electronic devices from silicon, a procedure for reducing surface recombination will usually be required for their functioning as well as for the application of various measurements and analytical methods. In particular, this is true for determining bulk recombination lifetime—which is a measure for the purity of silicon with regard to electrically active impurities. However, for the determination of this bulk recombination lifetime a necessary condition is that the smallest dimension of the sample must exceed four times the diffusion length of the free charge carriers. Generally, this requirement is not met by standard silicon wafers as their thickness is usually less than the diffusion length of the charge carriers. Only if the surface recombination velocity becomes sufficiently low, that is below 100 cm/s, will it be possible to measure bulk lifetime on standard silicon wafers with sufficient precision to monitor the purity of silicon wafers before and after technological processes for the device production.
A reduction of the surface recombination velocity in silicon can be achieved by thermally growing a silicon dioxide (SiO
2
) layer in an oxidizing atmosphere at temperatures in the range of about 800-1200° C. In the literature, and in common usage, such layers are also frequently designated by the more comprehensive heading “surface passivation”. In general, surface passivation also includes the additional aspect of “protection against environmental influences”. Due to the excellent mechanical, chemical, and electronic properties of the SiO
2
layer, today this type of layer is used in almost all areas of silicon semiconductor technology.
However, there are some applications where this type of layer cannot be used with satisfactory results. On the one hand, this is the case for devices which cannot withstand the high temperature-time stress occurring during the growth of this layer. Another case is the measurement of bulk lifetime in order to detect heavy metals in Si wafers in the ppb range. Here it is very difficult, or even impossible to quantify how oxidation will influence the heavy metal content of the wafer by additional contamination, or segregation, precipitation, and evaporation. On the one hand, depending on the ratio of contamination levels of wafer and oxidation furnace, contamination from the tube may diffuse into the wafer to be examined. But, on the other hand, it is also possible that contamination will outdiffuse from the wafer and accumulate in the oxide or precipitate homogeneously or heterogenously. In all these cases mentioned above, carrier lifetime measured subsequently no longer represents the original impurity level of the wafer. A further problem with thermal oxidation is the poor reproducibility of the density of states at the interface Si-SiO
2
, which determines the surface recombination velocity.
FIG. 5
illustrates the lifetime distribution of a thermally oxidized wafer, with a low average lifetime of 85.84 &mgr;s, which is mainly determined by the recombination at the Si-SiO
2
interface.
To overcome the problem of thermal stress, there is the possibility of using a SiO
2
layer deposited by the CVD (Chemical Vapor Deposition) process or one of its variants—PECVD (Plasma Enhanced CVD) or Photo CVD—instead of the thermally grown oxide layer. Depending on the process used, temperatures from approximately 100° C. to 900° C. are applied. A further advantage of these processes is that even layers such as silicon nitride Si
3
N
4
or silicon oxinitride SiO
x
N
y
can be deposited.
A serious disadvantage of these known deposited CVD layers is their poor ability to decrease the surface recombination velocity. Therefore they belong to the passivation layers in an extended sense, where the aspect “protection against environmental influences” takes precedence. For device applications, these layers will be used only in connection with a thin thermal SiO
2
layer grown directly onto the silicon surface. For the same reason, and due to the fact that there are equipment specific contamination problems, so far no relevant analytical applications are known.
The analytical application is further complicated by the fact that the diffusion coefficients of the impurity metals of interest in Si are mostly some orders of magnitude higher than those of the doping elements P, B, As, and Sb. Therefore temperature-time stress, which is tolerable even for highly sensitive devices, can cause unpredictable changes in the contamination level, as already mentioned in the context of thermal oxidation.
Furthermore, it is known that hydrogen and halogens (F, Cl, Br, J, and At) present at the Si surface will reduce surface recombination velocity. This can be achieved, for instance, by treating the Si surface with hydrofluoric acid (HF). A serious disadvantage of this method is that the reduction of surface recombination disapears under the influence of atmospheric oxygen within a few minutes after removing the wafer from the liquid. This precludes any device application. A known application in the analytical area is the “Elymat Method” for measuring charge carrier diffusion length in Si wafers. Here, the wafer is placed inside a cuvette containing diluted HF during the measurement.
Due to the hazards involved in handling HF, a rather large technical expense is required to reduce risks for the operating personnel.
A method which has become known more recently is to put the Si surfaces, freshly etched with HF, into an alcoholic iodine or bromine solution, as described e.g. by H. Msaad, J. Michel, J. J. Lappe and L. C. Kimmerling in “Electronic Passivation of Silicon Surfaces by Halogens” (to be published in “Journal of the Electrochemical Society” 1994). There, surface recombination velocities of less than 1 cm/s are achieved, which is an excellent value compared to about 100 cm/s achieved by thermal SiO
2
. A disadvantage of this method—just as with the previous one—is that the effect remains stable only as long as the wafer remains in the solution. An advantage is the considerably lower hazard potential involved in handling an alcoholic iodine solution, compared to HF. Nevertheless, handling the liquid involves a substantial additional effort.
SUMMARY OF THE INVENTION
The object of the invention is to provide a simple-to-implement process enabling the surface recombination velocity of silicon to be reduced to values less or equal 100 cm/s, and which also allows easy handling of Si devices or Si wafers treated with this process.
According to the invention there are the following steps:
First, the Si surface will be cleaned as each Si surface usually exhibits a silicon dioxide layer (SiO
2
) approximately 2 to 4 nm in thickness. Preferably, this SiO
2
layer can be removed by hydrofluoric acid (HF). After drying the Si surface, a lacquer will be applied to the surface of the Si wafer at a temperature of less than 100° C., preferably at ambient temperature, so that when this lacquer dries an electrically non-conducting layer is formed. This lacquer may be applied, for example, by spraying, spinning, painting, or even by dipping.
Depending on the type of lacquer used, the drying process will lead to a consolidation of the lacquer as, for instance, a solvent present in the lacquer will evaporate, and optionally and additionally a chemical reaction with a reacting partner from the layer or ambient atmosphere (such as atmospheric oxygen, humid air) will cause a gel to form or a change in the physical condition to occur, or cooling will convert lacquer applied at a temperature above ambient temperature into a firm layer. For analytical use of the process according to this invention, i.e. to measure the carrier lifetime of standard Si wafers, the applied layer must be transparent for the laser beam used to carry out measurements, e.g. in the 900 nm range.
By this manner, surface recombination velocity will be reduced to less than 100 c

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for manufacturing a silicon semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for manufacturing a silicon semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing a silicon semiconductor device... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2841766

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.