Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2000-06-07
2002-04-09
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S475000, C438S402000, C438S404000, C438S406000, C438S408000
Reexamination Certificate
active
06368938
ABSTRACT:
DESCRIPTION OF RELATED ART
Space and/or military operating environments for semiconductor devices (for example, CMOS devices) require that the transistors of these devices be resistant to radiation. Exposure to radiation can cause conventional devices, which are not radiation-hard to malfunction or destruct. It is recognized [
6
] that resistance to can be improved by fabricating devices on silicon-on-insulator (SOI) substrates. The small volume of silicon in the SOI layer improves the resistance to radiation-induced single-event upset. In addition, latch-up paths between adjacent devices (i.e., transistors) which are present in conventional bulk-semiconductor devices are eliminated in the SOI devices.
Although SOI technology has many advantages, it is a disadvantage relative to bulk silicon for hardness against total dose radiation [
6
]. The presence of the buried insulator layer creates an additional oxide that must be hardened. Because of its big thickness, sufficient amounts of positive charge are trapped in the buried insulator following total dose radiation. The charge accumulation results in increased device leakage and threshold voltage shifts.
Several methods of improving the total radiation dose hardness for SOI circuits are known. These techniques include the use of thicker silicon films and employing thinner buried oxides [
5
]. Due to the cited above review paper [
6
] by Johnson, partially depleted SOI devices have better radiation hardness than the fully depleted SOI. Thicker silicon films improve the total dose hardness because the film is only partially depleted. Thus, the gate charge is not coupled to the buried oxide charge.
This approach has the significant drawback that the body of the transistor is neutral and has a floating electrical potential. These results in the turn-on of the parasitic bipolar transistor formed by the source/body/drain of the device. To minimize the leakage caused by the transistor, the body of the transistor must be grounded either by a separate contact, or by a strap to the source. However, this results in a technology that is not compatible with bulk VLSI designs. Furthermore, many of the benefits of SOI, such as high transconductance, sharp transistor turn-on slopes, low power consumption, high speed action, shortened fabrication process, and circuit density improvements are lost with partially depleted SOI.
Another radiation hardening approach is to use thinner buried oxides [
5
]. However, in fully depleted structures, the front gate threshold voltage is capacitively coupled to the buried oxide [
6
]. Thus, thinning the buried oxide reduces the amount of charge that it traps, however, its capacitance goes up proportionally. Thus, essentially the same voltage shift is seen by the front gate.
In previous art, a method of forming a radiation hardened SOI structure is known due to U.S. Pat. No. 5,795,813 [
1
] by Hughes. Buried oxide of SOI is hardened. The radiation hardening is done by implantation of impurities that form recombination centers in the oxide. All the radiation hardening is done prior to the bonding of the device silicon layer. It prevents damage of the silicon device layer by the hardening process.
This conventional method is not effective enough. Under irradiation, holes and electrons are generated in the oxide. Then, electrons continue moving and they leave the oxide. Holes are not mobile and they are kept in the oxide. That holes cannot disappear on the recombination centers because of lack of electrons for them and because of lack of mobility. Holes remain in the oxide thus building up the positive charge.
A conventional radiation-hard, semiconductor device of SOI CMOS type is known according to U.S. Pat. No. 5,807,771 [
2
] by Vu et al. The radiation-hard semiconductor device includes heavy doped buried n-type and p-type wells in a first silicon layer over an insulator. Over the insulator, a second silicon layer is formed with congruent lightly-doped n-type and p-type layers in which complementary MOSFET active devices are formed. The heavy wells improve resistance to back-channel radiation-induced leakage due to (1) partially-depleted regime ensured by the heavy wells, and (2) gettering function of the wells. The gettering mostly prevents yield drop, but it also affects indirectly on the radiation hardness of the SOI. The final SOI devices have more uniform characteristics from device to device. Integrated semiconductor device fails under irradiation upon fail of the weakest from the devices. The uniform characteristics mean absence of weak devices.
A disadvantage of this process is that it improves only semiconductor part of the integrated semiconductor device while the final radiation hardness is limited by the dielectric parts of the integrated semiconductor device.
A process for preventing yield drop in fabrication of SOI semiconductor devices due to heavy metal contamination is described in U.S. Pat. No. 5,753,560 [
3
] by Hong. The process uses lateral gettering of the contaminants.
Disadvantage of the process [
3
] is that gettering technique used is not effective enough. Lateral gettering is not as effective as proximity gettering. In addition, lateral gettering has an inherent drawback because forming of special areas in SOI top film are required. That special areas work as a getter. It decrease the maximum achievable packing density of transistors, increase number of processing steps, and fabrication costs.
As it was mentioned above, the gettering improves the radiation hardness indirectly. The performance of a semiconductor device is affected by impurities in the semiconductor substrate on which the semiconductor device is fabricated. For example, the presence of metallic impurities such as copper, nickel, iron, chromium, molybdenum, etc. tends to introduce generation-recombination centers in the energy band gap and degrade the integrity of the oxide layer formed on the semiconductor substrate, thereby affecting the performance of the semiconductor device. Impurity gettering can be performed to reduce impurities in a region of the semiconductor substrate where the semiconductor device is fabricated. Conventionally, impurity gettering includes intrinsic gettering and extrinsic gettering processes as it is described in a book Gettering and Defect Engineering in Semiconductor Technology by Herbert P. Richter, Enfield Publishers, 660 pages, 1992. In an intrinsic gettering process, gettering sinks, such as crystal defects or oxygen precipitates, are formed in the semiconductor substrate at a distance from the front side of the substrate, wherein the distance is greater than the depth of semiconductor devices fabricated in the substrate. The substrate is heated to aid the diffusion of impurities in the substrate. As the impurities diffuse, they are trapped or absorbed by the gettering sinks. In an extrinsic gettering process, a gettering sink, such as a polycrystalline silicon layer, is formed on the backside of the substrate. The semiconductor substrate is heated to aid the diffusion of impurities in the substrate. As the impurities diffuse, they are trapped or absorbed by the gettering sink formed on the backside. Therefore, after either the intrinsic or the extrinsic process, the impurity concentration near the front side of the substrate decreases.
However, the gettering processes described in the cited book Gettering and Defect Engineering in Semiconductor Technology by Herbert P. Richter, Enfield Publishers, 660 pages 1992 are designed for bulk silicon substrates. They are ineffective for a semiconductor-on-insulator substrate. A semiconductor device fabricated on a SOI substrate typically extends from the front side of the substrate to the buried insulator layer. Accordingly, the gettering sinks, either intrinsic or extrinsic, are formed below the buried insulator layer, which is a diffusion barrier to some impurities in the substrate. In a conventional fabrication process in which the temperatur
Dang Trung
Silicon Wafer Technologies Inc.
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