Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-05-17
2003-09-02
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S745000, C438S753000
Reexamination Certificate
active
06613678
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor substrate as well as a semiconductor thin film. More particularly, it relates to processes for manufacturing a semiconductor substrate which has a single-crystal semiconductor layer on an insulator layer, and a single-crystal compound semiconductor which overlies a Si (silicon) substrate. Further, it relates to a multilayer structure suitable for an electron device or an integrated circuit which is to be produced in a single-crystal semiconductor layer, and a process for manufacturing the multilayer structure.
2. Related Background Art
The formation of a single-crystal Si semiconductor layer on an insulator has been extensively known as “silicon on insulator (SOI)” technology. Since devices utilizing the SOI technology have numerous advantages unattainable with conventional bulk Si substrates for producing Si integrated circuits (ICs), many researches have been made. More specifically, the utilization of the SOI technology brings forth such advantages as follows:
(1) Dielectric isolation is easy enough to heighten the density of integration.
(2) A resistance against radiation is excellent.
(3) A stray capacitance can be lowered to achieve a higher operating speed.
(4) The steps of forming wells can be dispensed with.
(5) The device can be prevented from latching up.
(6) A fully depleted FET (field-effect transistor) can be produced owing to thinned films.
(These features are detailed in, for example, Special Issue: “Single-crystal silicon on non-single-crystal insulators” edited by G. W. Cullen, Journal of Crystal Growth, volume 63, no. 3, pp. 429-590 (1983).)
Further, in recent several years, SOI has been reported in a large number of papers as a substrate which realizes the higher operating speed and lower power dissipation of a MOSFET (Metal-Oxide-Semiconductor FET) (IEEE SOI Conference 1994).
Besides, with an SOI structure wherein a supporting substrate is overlaid with an SOI layer through an insulator layer, the insulator layer comes to exist under circuit elements, and hence, an element isolating process can be simplified as compared with that in the case of forming elements on a bulk Si wafer. As a result, a process for producing a device which employs the SOI structure is shortened.
That is, a MOSFET or an IC which is produced on the SOI is expected of, conjointly with enhancement in performance, curtailment in a wafer cost and a process cost in total as compared with that which is produced on bulk Si.
Among all such devices, the fully depleted (FD) MOSFET is expected to heighten its operating speed and lower its power dissipation owing to an enhanced driving force. In general, the threshold voltage (V
th
) of a MOSFET is determined by the impurity concentration of the channel thereof. In the case of the FD MOSFET employing the SOI, however, the thickness of the depletion layer thereof is also affected by the film thickness and film quality of the SOI.
Accordingly, uniformity in the thickness of an SOI film and enhancement in the quality of the SOI film have been eagerly desired for producing a large-scale integrated circuit (LSI) at a good available percentage.
Researches on the formation of SOI substrates have been vigorous since the 1970's. Earnestly studied at the early stage were a process (SOS: Silicon on Sapphire) wherein single-crystal Si is hetero-epitaxially grown on a sapphire substrate being an insulator, a process (FIPOS: Full Isolation by Porous Oxidized Silicon) wherein an SOI structure is formed by dielectric isolation based on the oxidation of porous Si, and oxygen ion implantation.
Apart from the processes for forming the SOI substrates as mentioned above, processes for forming SOI substrates as are called “bonding or adhesion techniques” have been being established in recent years.
One of the bonding techniques is stated by M. Bruel in “Electronics Letters, 31 (1995), p. 1201”, the official gazette of Japanese Patent Application Laid-Open No. 5-211128, and U.S. Pat. No. 5,374,564.
This bonding technique is a process termed “Smart Cut Process” (registered trademark), which consists chiefly of five steps and which will be explained below in conjunction with the drawings.
(First Step) A first silicon substrate (bulk wafer)
41
having an oxide film
43
on its surface is prepared as shown in FIG.
24
.
(Second Step) The first silicon substrate
41
is implanted with hydrogen ions from the side of the oxide film
43
(FIG.
25
). The hydrogen ions are implanted down to a desired depth at which the substrate
41
is to be separated by the later step. A layer
44
of minute gaseous bubbles called “microbubbles” or “microblisters” is formed in a region implanted with the hydrogen ions.
(Third Step) The resulting first silicon substrate
41
and a second substrate
46
to become a supporting substrate are bonded to each other so that the oxide film
43
may lie inside (FIG.
26
).
(Fourth Step) After the bonding, the resulting structure is heat-treated at low temperatures of 400° C. to 600° C. or so. Then, as shown in
FIG. 27
, the first substrate
41
having been bonded on the second substrate
46
is separated or divided with the boundary at the minute bubble layer
44
. More specifically, the heat treatment rearranges the crystals of the minute bubble layer
44
and also causes the microbubbles to coalesce, whereby gaseous macrobubbles are produced. Pressures within the macrobubbles act to highly stress the minute bubble region and the vicinity thereof. Consequently, the substrate
41
is separated at the bubble layer
44
.
(Fifth Step) Thereafter, the resulting structure which includes the supporting substrate
46
is heat-treated at high temperatures in order to stabilize the interface of the bonding and to heighten the strength thereof. Subsequently, the minute bubble layer
44
which remains on an SOI layer
42
as shown in
FIG. 27
is polished away as shown in FIG.
28
.
Via the above steps, the first silicon substrate (bulk wafer) is partly transferred onto the second substrate, and the SOI substrate can be obtained.
In the case where the SOI layer is formed by utilizing the implantation with the ions of hydrogen or the like as stated above, the ion-implanted region substantially determines the thickness of the SOI layer. It is therefore important how the desired implantation region (thickness of the SOI layer) is defined at a high controllability.
Besides, since the SOI layer itself is formed on the basis of the bulk wafer, it involves defects or flaws peculiar to the bulk wafer, such as OSFs (Oxidation Induced Stacking Faults), COPs (Crystal Originated Particles) and FPDs (Flow Pattern Defects).
Herein, the defects of the OSFs etc. form causes for increasing a leakage current when they exist in an element operation region near the surface of the wafer. It has therefore been desired to establish a process for manufacturing an SOI substrate which is free from the OSFs etc. or in which the OSFs etc. are less.
By the way, the OSFs and COPs (Hidekazu Yamamoto: “Problems of Large-diameter Silicon Wafer to be Solved”, 23rd Ultraclean Technology College (August 1996)) and the FPDs (T. Abe: Extended Abst. Electrochem. Soc., Spring Meeting, vol. 95-1, p. 596 (May, 1995)) will be explained later.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a process for manufacturing a semiconductor thin film which is smaller in the number of defects and whose thickness is highly uniform.
Another object of the present invention is to provide a process for manufacturing an SOI substrate in which the thickness of an SOI layer is highly uniform.
Another object of the present invention is to provide a process for manufacturing a semiconductor thin film which is free from defects peculiar to a bulk silicon wafer, such as OSFs, COPs and FPDs, or in which they are less.
Still another object of the present invention is to provide a process for manufacturing an SOI substrate which is made more economical by reusing a
Sakaguchi Kiyofumi
Sato Nobuhiko
Yonehara Takao
Deo Duy-Vu
Fitzpatrick ,Cella, Harper & Scinto
LandOfFree
Process for manufacturing a semiconductor substrate as well... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for manufacturing a semiconductor substrate as well..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for manufacturing a semiconductor substrate as well... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3056103