Process for manufacturing a semiconductor device

Details Process for manufacturing a semiconductor device Process for manufacturing a semiconductor device

2000-01-06

2003-07-08

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S712000, C438S742000

Reexamination Certificate

active

06589873

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a process for manufacturing a semiconductor device. In particular, it relates to a process for forming a contact for electrically connecting a device with a wiring.
2. Description of the Related Art
For electrically connecting an MOSFET device with another device or an external electric terminal, on a semiconductor substrate is formed an MOSFET, on which is formed an interlayer insulating film; then a contact hole is opened in the interlayer insulating film to expose the source, the drain and the gate electrodes of the MOSFET; and the opening is filled with a conductive material to form a contact, on which wirings are then formed.
FIGS. 8 and 9
show an example of the process.
FIG. 8
is a cross-section along the channel in the MOSFET structure.
FIG. 9
is a cross-section along the direction perpendicular to the channel in FIG.
8
.
As shown in FIGS.
8
(
a
) and
9
(
a
), an MOSFET device comprising a gate oxide film
303
, a polycide structure of gate electrode
304
consisting of a polysilicon film
305
and a tungsten-silicide film
306
, a sidewall
308
on the sidewall of the gate electrode, and a source-drain region
307
is formed on a device region of a p-type silicon substrate
301
which is delimited by a device-separating silicon oxide film
302
.
As shown in FIGS.
8
(
b
) and
9
(
b
), a BPSG film
309
is formed as an interlayer insulating film and then contact holes
311
reaching the source-drain region
307
and the gate electrode
304
are formed. As seen in the cross section of FIG.
9
(
b
), the contact hole is formed over an brig-out area rather than just over the channel for the gate electrode.
As shown in FIGS.
8
(
c
) and
9
(
c
), a titanium film
312
is formed on the BPSG film surface including the sidewall of the contact holes, on the source-drain region and the gate electrode each exposed in the contact holes. In the process, silicon reacts with titanium on the surfaces of the source-drain region and the gate electrode to form a titanium silicide film
313
, which contributes to decrease contact resistance with the contact plug.
As shown in FIGS.
8
(
d
) and
9
(
d
), a titanium nitride film
314
is formed by thermal CVD on the whole surface, filling at least the contact holes. The titanium nitride film is etched back to form plugs, leaving the film only in the contact holes
311
. An aluminum-alloy film is formed and then patterned by etching to form upper wirings
315
shown in FIGS.
8
(
e
) and
9
(
e
). The source-drain region and the gate electrode of the MOSFET are connected to another device or an external terminal via the upper wirings
315
.
In the process for manufacturing a semiconductor device, the titanium film shown in FIG.
8
(
c
) or
9
(
c
) is formed by plasma CVD because of the following reasons. For example, spattering cannot form an even film both on the bottom and the sidewall of the contact holes. Furthermore, when TiCl
4
and H
2
are used as reactants, thermal CVD requires a higher substrate temperature of 1000° C. while plasma CVD requires about 600° C.
In conventional plasma CVD, RF power is applied in a chamber in which Ar and H
2
gases have been introduced, to generate plasma. After the plasma almost becomes stable, e.g. after 1 to 5 sec, introduction of TiCl
4
gas is initiated to form a titanium film.
The process, however, has a problem that when generating plasma from Ar and H
2
charge is accumulated on an interlayer insulating film such as the BPSG film
309
as shown in FIG.
10
and may cause a large potential difference between the gate electrode
304
and the silicon substrate
301
, leading to electric breakdown in the gate oxide film
303
. Particularly, as a device has been miniaturized, a gate oxide film has become thinner and the antenna ratio of the gate electrode, i.e., the ratio defined by dividing the total area of the gate electrode by the area of the gate electrode over the channel region, has been increased, more frequently causing electric breakdown in the gate oxide film. For example, electric breakdown during plasma CVD is negligible for a gate oxide film 150 Å in thickness while eminent at about 100 Å. Furthermore, as the aspect ratio (i.e., depth/diameter) of the contact hole becomes larger, charge imbalance referred to as a shading effect becomes more eminent as shown in
FIG. 10
, more frequently causing electric breakdown in the gate oxide film.
SUMMARY OF THE INVENTION
In the light of these problems, an objective of this invention is to provide a process for manufacturing a semiconductor device where even for a high-density and highly-integrated device, a gate oxide film is not damaged during forming a metal film in a contact hole by plasma CVD, and a plasma CVD apparatus used therefor.
This invention provides a process for manufacturing a semiconductor device comprising the step of forming a metal film by plasma CVD in a contact hole which penetrates an interlayer insulating film covering a given device formed on a semiconductor substrate and which reaches an electrode of the device, wherein the metal film is formed in the contact hole by introducing a gas comprising hydrogen and argon in a deposition chamber of a plasma CVD apparatus and then introducing a metal halide gas in the deposition chamber simultaneously with or before plasma generation.
This invention also provides a plasma CVD apparatus for the manufacturing process for a semiconductor device, comprising a synchronization/delay mechanism whereby the metal halide gas is introduced simultaneously with or before turning RF power on for plasma generation.


REFERENCES:
patent: 5177589 (1993-01-01), Kobayashi et al.
patent: 5508066 (1996-04-01), Akahori
patent: 5747384 (1998-05-01), Miyamoto
patent: 5942282 (1999-08-01), Tada et al.
patent: 6174805 (2001-01-01), Urabe
patent: 6177149 (2001-01-01), Tada et al.
patent: 09-205070 (1997-08-01), None
patent: 10-298768 (1998-11-01), None
patent: 11-16858 (1999-01-01), None
patent: 11-186197 (1999-07-01), None

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