Process for manufacturing a dynamic random access memory cell

Fishing – trapping – and vermin destroying

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437 45, 437 47, 437 52, H01L 27108, H01L 21265

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active

049450662

ABSTRACT:
A process for manufacturing a dynamic random access memory (DRAM) cell wherein an improvement is made in an occurrence of soft errors in operation of a memory device, said soft errors resulting from alpha particles being produced from uranium-series materials included in fabricating materials during fabrication of memory chips, especially in the package of the chip. In a single transistor memory cell, through forming boron layers below a storage capacitor region and below a drain region of the transistor coupled with a bit line, a barrier is formed against the minority carriers resulting from the alpha particles within the substrate. Also, through enlarging the storage capacitor region toward a field oxide layer just around the capacitor perimeter, a capacitance of the storage capacitor is increased so that the influence of the soft errors is negligible.

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