Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-07
2004-11-30
Lee, Hsien Ming (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S324000, C257S332000, C438S259000, C438S261000, C438S262000, C438S265000, C438S267000
Reexamination Certificate
active
06825523
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
The present application claims priority from European patent application no. 01830634.0, filed Oct. 8, 2001, entitled PROCESS FOR MANUFACTURING A DUAL CHARGE STORAGE LOCATION MEMORY CELL, presently pending.
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of semiconductor memories, particularly non-volatile memories and still more particularly to electrically programmable non-volatile memories. More specifically, the invention concerns dual charge storage location non-volatile semiconductor memory cells and, in particular, the manufacturing thereof.
As known, the information storage mechanism in non-volatile memory cells such as EPROMs, EEPROMs and Flash EEPROMs is based on the possibility of having an electric charge trapped in a charge storage element. The presence of the electric charge in the charge storage element causes a change in the memory cell threshold voltage, that can be assessed by measuring a current sunk by the memory cell in a prescribed bias condition.
Typically, the charge storage element is represented by a polysilicon floating gate insulatively placed over the memory cell channel region and capacitively coupled to a control gate. Charge carriers can be injected into the floating gate by means of the hot electron injection mechanism, as in EPROMs and Flash EPROMs, or by tunnelling, as in EEPROMs. The presence of an electric charge in the floating gate affects the formation of a conductive channel in the channel region.
Up to some years ago, each memory cell was used to store one bit of information, corresponding to the absence of charge in the floating gate (a condition conventionally interpreted as a logic “1”) or the presence (logic “0”) in the floating gate of an electric charge equal to or greater than a prescribed minimum amount.
The constant trend towards the increase of semiconductor memory storage capacity per unit chip area has however suggested that each memory cell could be used to store more than one bit.
Memory cells have therefore been proposed having multiple threshold voltage levels. In such memory cells, commonly referred to as multi-level memory cells, the amount of charge trapped in the floating gate is precisely controlled and can take more than two values, for example four. To each value of electric charge there corresponds a respective threshold voltage of the memory cell. A multi-level memory cell having for example four admissible threshold voltages is able to store two bits.
More recently, memory cells having two charge storage locations have been proposed. In these memory cells it is possible to have an electric charge trapped in two physically distinct locations of the memory cell, normally at each side of the channel region thereof, near the source/drain regions.
Two types of dual charge storage location memory cells are known in the art.
A first type of dual charge storage location memory cell is described for example in U.S. Pat. No. 5,949,711. The memory cell comprises a control gate insulatively placed over a channel region. At both sides of the control gate, near the source/drain diffusions, two electrically isolated spacers of polysilicon form two floating gates.
Charge can be selectively injected into each floating gate and be trapped therein. Each floating gate controls a short portion of the memory cell channel.
Each one of the source/drain diffusions acts as a source electrode when reading the value of the charge trapped in the adjacent floating gate, and as a drain electrode when reading the value of the charge trapped in the opposite floating gate.
As the traditional single bit or multi-level memory cells having a single floating gate, this dual charge storage location memory cell relies for its operation on the capacitive coupling between the control gate and the two floating gates.
However, due to the physical location of the two floating gates at the sides of the control gate, the areas of coupling between the latter and the former are rather small. The capacitive coupling between the control gate and the floating gate is therefore scarce, thus allowing a small amount of charge to be injected.
A second type of dual charge storage location memory cells is described for example in U.S. Pat. No. 6,201,282 B1. In this case the memory cell comprises a control gate insulatively placed over a channel region with interposition of an oxide-nitride-oxide (ONO) stack of layers. Charge can be injected into and trapped in two separated and separately chargeable areas found within the nitride layer, near the memory cell source/drain regions. The latter, as in the dual charge storage location memory cell described above, change their role while reading the charge trapped in one or the other of the two areas.
Compared to the one previously described, this dual charge storage location memory cell requires one less polysilicon layer, which simplifies the manufacturing process. However, this structure is affected by problems of confinement of the charge in the two areas within the nitride layer. It is in fact difficult to keep the two charges separated, since there is no physical separation therebetween. This problem arises in the memory cell writing and erasing operations, as well as during the memory cell life, and may cause the loss of the stored information.
In U.S. Pat. No. 6,248,633 B1 a dual charge storage location memory cell with a twin MONOS structure is disclosed. The memory cell comprises two polysilicon sidewall control gates placed over a composite ONO stack on both sides of a polysilicon word gate. The latter is placed over a gate oxide layer.
The nitride within the ONO stack of layers which is under each sidewall control gate is the region for electron memory storage. Since the two nitride layer regions under the two sidewall control gates are physically separated from each other, this structure appears not to be affected by the problem of charge confinement previously discussed.
However, the various processes for manufacturing the MONOS dual charge storage location memory cell described in that document appear to the Applicant rather complicated. For example, use is made of disposable polysilicon sidewall spacers to fabricate the memory cell channel, which increases the process steps.
In view of the state of the art described, it has been an object of the present invention to provide an alternative manufacturing process for a dual charge storage location electrically programmable memory cell.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a process for manufacturing a dual charge storage location electrically programmable memory cell. The process provides for forming a central insulated gate over a semiconductor substrate; forming physically separated charge confining stack portions of a dielectric-charge trapping material-dielectric layers stack at the sides of the central gate, the charge trapping material layer in each charge confining stack portion forming a charge storage element; forming side control gates over each of the charge confining stack portions; forming memory cell source/drain regions laterally to the side control gates; electrically connecting the side control gates to the central gate.
Each of the charge confining stack portions at the sides of the central gate is formed with an “L” shape, with a base charge-confining stack portion lying on the substrate surface and an upright charge confining stack portion lying against a respective side of the central gate.
According to another aspect of the present invention, there is provided a process for manufacturing an array of dual charge storage location electrically programmable memory cells.
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patent: 5408115 (1995-04-01), Chang
patent: 5949711 (1999-09-01), Kazerounian
patent: 6201282 (2001-03-01), Eitan
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6413821 (2002-07-01), Ebina et al.
patent: PCT/US00/23484 (2001-03-01), None
Patent Abstracts Of Japan. vol. 2000, No. 23, Feb. 10, 20
Brambilla Claudio
Caprara Paolo
Cereda Manlio Sergio
Born P. G. Scott
Graybeal Jackson Haley LLP
Jorgenson Lisa K.
Lee Hsien Ming
STMicroelectronics S.r.l.
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