Process for making multilayer integrated circuit substrate

Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board

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427250, 427255, 4272557, 427318, 427 88, 427 89, 427 91, 357 71, 204192C, B05D 512

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043861164

ABSTRACT:
A process is provided for making a multilayer integrated circuit substrate having improved via connection. A first layer M1 of chrome-copper-chrome is applied to a ceramic substrate and the circuits etched. A polyimide layer is then applied, cured, and developed and etched to provide via holes in the polyimide down to the M1 circuitry. The top chrome is now etched to expose the M1 copper in the via holes. A second layer M2 of copper-chrome is evaporated onto the polyimide at a high substrate temperature to provide a copper interface at the base of the vias having no visable grain boundaries and a low resistance. M2 circuitization is then carried out.

REFERENCES:
patent: 3204158 (1965-08-01), Schreiner et al.
patent: 3881884 (1975-05-01), Cook et al.
patent: 4046660 (1977-09-01), Fraser
J. Gow III et al., Process for Making Multilayer IC Substrate, IBM TDB, vol. 22, No. 4, Sep. 1979, pp. 1420-1421.
Abolafia, Method of Connecting Layers of Circuitry Separated by a Dielectric, IBM TDB, vol. 22, No. 10, Mar. 1980, pp. 4471-4473.

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