Process for making fine pitch connections between devices...

Details Process for making fine pitch connections between devices... Process for making fine pitch connections between devices...

2006-05-23

2006-05-23

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S712000, C257S713000, C257S707000, C257S778000, C257S724000, C257S774000, C257S737000

Reexamination Certificate

active

07049697

ABSTRACT:
A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

REFERENCES:
patent: 4670770 (1987-06-01), Tai
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4884122 (1989-11-01), Eichelberger et al.
patent: 4933042 (1990-06-01), Eichelberger et al.
patent: 4949148 (1990-08-01), Bartelink
patent: 5019535 (1991-05-01), Wojarowski et al.
patent: 5258236 (1993-11-01), Arjavalingam et al.
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5373627 (1994-12-01), Grebe
patent: 5870289 (1999-02-01), Tokuda et al.
patent: 5998868 (1999-12-01), Pogge et al.
patent: 6025638 (2000-02-01), Pogge et al.
patent: 6066513 (2000-05-01), Pogge et al.
patent: 6087199 (2000-07-01), Pogge et al.
patent: 6110806 (2000-08-01), Pogge
patent: 6130823 (2000-10-01), Lauder et al.
patent: 6355501 (2002-03-01), Fung et al.
patent: 6586835 (2003-07-01), Ahn et al.
patent: 1041624 (2000-10-01), None
J. Pilchowski et al., “Silicon MCM with Fully Integrated Cooling,” HDI Magazine, May 1998, p. 48.
J. Wolf et al., “System Integration for High Frequency Applications,” Intl. J. of Microelectronics and Electronic Packaging 21, 119 (1998).
C.A. Armiento et al., “Gigabit Transmitter Array Modules on Silicon Waferboard,” IEEE Transactions on Components, Hybrids and Manufacturing Technology 15, 1072 (1992).
M. Töpper et al., “Embedding Technology—A Chip-First Approach Using BCB,” 1997 Intl. Symposium on Advanced Packaging Materials, p. 11.
Jeffrey T. Butler et al., “Advanced Multichip Module Packaging of Micromechanical Systems,” 1997 Intl. Conf. on Solid-State Sensors and Actuators, p. 261.
Robert Boudreau et al., “Wafer Scale Photonic-Die Attachment,” IEEE Trans. on Components, Packaging and Manufacturing Technology-Part B, 21, 1070 (1998).
Z. Xiao et al., “Low Temperature Silicon Wafer-to-Wafer Bonding with Nickel Silicide,” J. Electrochem. Soc. 145, 1360 (1998).
R. Fillion et al., “Plastic Encapsulated MCM Technology for High Volume, Low Cost Electronics,” Circuit World 21, 28 (1995).
“A Novel Chip-Stack Package”—Solid State Technology, Apr. 2002, www.solid-state.com, pp. S19-S22, Eric Beyne, IMEC, Leuven, Belgium.

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