Process for making a transistor with self-aligned source and dra

Details Process for making a transistor with self-aligned source and dra Process for making a transistor with self-aligned source and dra

1997-08-14

1999-06-15

Chaudhuri, Olik

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438453, 438233, 438449, 438297, 438225, H01L 2128

Patent

active

059131365

ABSTRACT:
The invention relates to a process for making a transistor with self-aligned contact points and comprises the following steps: formation of multiple layers on a substrate (100) and etching of the multiple layers using a first mask, but preserving a column of the multiple layer; formation of lateral spacers on the sides of the column and implantation of impurities; local oxidation of the silicon substrate within the implanted region and elimination of the lateral spacers; deposit of a layer of insulating material (130) surrounding the column; etching of the column in accordance with a second mask to form a grid structure (140) with second sides, and exposing third sides delimiting the active region; formation of self-aligned insulating spacers (142, 143) on the second and third sides, and implantation of the source and drain (150, 152); formation of contact points (160, 162).

REFERENCES:
patent: 4461072 (1984-07-01), Wada et al.
patent: 4708768 (1987-11-01), Enomoto et al.
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5550071 (1996-08-01), Ryou
patent: 5612247 (1997-03-01), Itabashi
patent: 5773346 (1998-06-01), Manning

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