Process for making a small dynamic memory cell structure

Details Process for making a small dynamic memory cell structure Process for making a small dynamic memory cell structure

1984-07-02

1986-09-02

Kimlin, Edward

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156657, 1566591, 29571, 29576B, 29578, 148 15, H01L 21265, H01L 21302

Patent

active

046094296

ABSTRACT:
A process is provided for making a conductive structure for a semiconductor circuit, such as a one device dynamic random access memory cell, which includes the steps of depositing a conductive layer on a surface of a semiconductor substrate having a given type conductivity spaced from a storage node, depositing a layer of polysilicon over the conductive layer, depositing a layer of photoresist over the polysilicon layer, defining an opening in the photoresist layer and implanting ions of a conductivity type opposite to that of the given type conductivity through the opening and the polysilicon layer into the semiconductor substrate to form therein a conductive pocket or region having the opposite type conductivity resulting in, e.g., a highly conductive bit/sense line of a memory cell.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3811076 (1974-05-01), Smith, Jr.
patent: 3841926 (1974-10-01), Garnache et al.
patent: 4343082 (1982-08-01), Lepselter et al.
patent: 4365405 (1982-12-01), Dickman et al.
patent: 4398341 (1983-08-01), Geipel, Jr. et al.
IBM Technical Disclosure Bulletin, vol. 21, No. 9, Feb., 1979, pp. 3823-3825, "Double Polysilicon Dynamic Random-Access Memory Cell with Increased Charge Storage Capacitance", by V. L. Rideout.
Johnson, Jr. et al., "Etch Stop for R.I.E. of Polysilicon", IBM Tech. Discl. Bull., vol. 21, No. 2, Jul. 1978, pp. 599-600.
Howard et al., "Process for SBD Metallurgies", IBM Tech. Discl. Bull., vol. 22, No. 5, Oct. 1979, pp. 1823-1824.

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