Process for making a gate for a short channel CMOS...

Details Process for making a gate for a short channel CMOS... Process for making a gate for a short channel CMOS...

2003-09-08

2004-11-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S182000, C438S286000, C438S585000, C438S704000, C438S696000, C438S712000, C438S713000, C257S388000, C257S344000

Reexamination Certificate

active

06818488

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a process for making a gate for a short channel CMOS transistor structure.
STATE OF PRIOR ART
The polysilicon gate is the heart of a CMOS device. In a traditional approach, the gate is obtained by chaining a photolithography step followed by an etching step. The photolithography step defines the required dimension in a resin mask. The image obtained in the resin is then transferred by plasma into a polysilicon or amorphous silicon layer, usually doped. This step is carried out in a high-density plasma etching reactor. The gate manufacturing step is of primary importance since the dimension of the gate fixes the device operating speed. As a general rule, a deviation of the dimension up to 10% of the target dimension is authorized. A special effort is made to obtain perfectly straight etching sides (anisotropic etching) during the etching step, such that the dimension of the polysilicon at the bottom of the gate is equal to the dimension of the polysilicon at the top of the gate, itself fixed by the mask dimension to the first order of magnitude. This is illustrated by
FIG. 1
that shows a cross section of part of a CMOS transistor structure being made. A resin mask
1
(or a hard mask) enabled the formation of a gate
2
from a polysilicon, amorphous silicon or SiGe alloy layer deposited on a silicon substrate
3
covered by a layer of gate oxide
4
.
If the gate etching is anisotropic, the photolithography step is used to obtain the required gate dimension. This approach has been used for more than 40 years in microelectronics. Progress in lithography has made it possible to reduce the dimension of the transistor gates and therefore to increase their operating speed.
This type of polysilicon gate may be etched by chaining several different etching steps, with the objective of obtaining straight etching sides to respect the dimension defined by the lithography step as accurately as possible. The process usually comprises at least three steps, each of which performs a very precise role.
The first step is a breakthrough step that eliminates the native oxide present on the surface of the polysilicon before etching. This step is carried out under conditions which optimise elimination of this native oxide: high source power, strong polarization of the substrate holder. This step only lasts a few seconds since it is not very selective with respect to the gate mask and therefore causes its consumption.
The second step, called the main etching step, quickly etches the polysilicon and defines the etching anisotropy. It is generally done with gas mixtures such as Cl
2
/O
2
, HBr/Cl
2
/O
2
or HBr/O
2
. The presence of oxygen in the gas phase of the plasma enables the formation of silicon, oxygen and bromine or chlorine based etching products, depending on which mix is used. These etching products are deposited on the sides of the polysilicon while it is being etched. These non-volatile products only form when the energy of ions bombarding the substrate is greater than 70-80 eV. Therefore the polarization power applied to the substrate holder has to be adapted to the plasma density to enable the formation and atomisation of these etching products. The accumulation of etching products deposited on the sides of the polysilicon generates a passivisation layer that protects the sides of the polysilicon from spontaneous reactive chemical attack by neutral species of plasma (atomic chlorine or atomic bromine or excited atomic chlorine and bromine). For Cl
2
/O
2
, HBr/Cl
2
/O
2
or HBr/O
2
type plasmas, surface analyses by X photoelectron spectroscopy show that the passivisation layer that forms during the main etching step is of the SiO
x
Cl
y
Br
z
type, where x, y and z<1. It may be compared with a porous silicon oxide substoichiometric in oxygen but rich in bromine (in the case of an HBr/O
2
chemistry) or in chlorine (in the case of a Cl
2
/O
2
chemistry). Its thickness is greater at the top of the gate (typically between 5 and 10 nm) than at the bottom of the gate (of the order of 1 to 2 nm). The thickness and the chemical composition of the passivisation layer depend on the mix of the etching gases and operating conditions of the plasma (RF power injected into the source, RF polarisation power applied to the substrate holder, working pressure, etching gas flow).
FIG. 2
shows the formation of a passivisation layer while the polysilicon layer is being etched. This figure shows the gate
2
in
FIG. 1
during manufacturing by etching a polysilicon layer
5
. A passivisation layer
7
is formed on the sides of the gate being formed under the action of the ions
6
that bombard the polysilicon layer with sufficient energy.
The third step is the over-etching step. This eliminates polysilicon residues that remain, if any, after the main etching step in the dense lines of small polysilicon. Its duration is of the order of 30 to 100% of the duration of the main etching step. During the over-etching step, the polarization power applied to the substrate holder is reduced to that applied during the main etching step (typically by a factor of 2) so as not to damage the gate oxide that protects the silicon substrate from structural and electrical damage that could be caused by the plasma. During the over-etching step, the passivisation layer is no longer supplied by etching products. The passivisation layer may then be eroded or completely etched by active species of the plasma (atomic chlorine, atomic bromine). In this case, the polysilicon is exposed to the active species. The resulting spontaneous etching reactions can cause severe distortions of the etching profiles. Therefore, in a standard etching process, if the anisotropy of the etching is to be perfect, the passivisation layer formed during the main etching step needs to be resistant enough so that it is not fully consumed while it is exposed to the over etching plasma.
The main etching step may possibly be separated in two distinct steps. A first step is identical to the step described previously. It is applied during about the ⅔ or the ⅘ of the thickness of the polysilicon layer. The RF polarization power applied to the substrate holder to etch the remaining thickness of polysilicon is very much reduced, within a range of values identical to that applied during the over etching step, so that the gate oxide is reached under mild plasma (landing step) conditions in order to minimize its consumption.
Table I shows an example of the use of the etching process for a process comprising a main etching step in two parts (main etching I and main etching II). In this example, it is considered that the plasma is a high-density inductive source capable of etching 200 mm substrates and that the power injected in the source is of the order of 500 W. The result is that the plasma density is of the order of 10
11
ions/cm
3
. The gas flows indicated and the working pressure are only given as examples. It is quite clear that the flows indicated for each gas can vary within a fairly wide range. The value of the RF power, called P, applied to the substrate holder in each step is only given for guidance. These values are different if the power injected in the source is different.
In this table, the gas flows are expressed in “sccm”, in other words in normal cm
3
/minute. The pressure is expressed in mTorr for practical reasons (1 mTorr=approximately 0.133 Pa).
TABLE I
Chemistry
in gaseous
Gas flow
Step
phase
Pressure
P (W)
Breakthrough
C
2
F
4
or Cl
2
100 sccm
P > 200
a few mTorr
Main etching I
HBr/Cl
2
/O
2
150/30/5 sccm
80 < P < 150
a few mTorr
Main etching II
HBr/Cl
2
/O
2
150/30/5 sccm
40 < P < 70
a few mTorr
Over-etching
HBr/O
2
150/10 sccm
40 < P < 60
> 30 mTorr
Recently, the specialized literature has started to include references to CMOS transistor structures with a notched gate bottom. For example, this is the case in article “100 nm Gate Length High Performance/Low Power CMOS Transistor Structure” by T. GHANI et al. published in the IEDM 1999 revie

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