Process for low energy implantation of semiconductor substrate u

Details Process for low energy implantation of semiconductor substrate u Process for low energy implantation of semiconductor substrate u

1996-04-12

1999-05-18

Tsang, Cecilia J.

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

438515, 438526, 438529, H01L21/265;21/70

Patent

active

059045515

ABSTRACT:
A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

REFERENCES:
patent: 4710477 (1987-12-01), Chen
patent: 5393689 (1995-02-01), Pfiester et al.
Wolf & Tauber, "Silicon Processing for the VLSI Era" vol. 1 (Lattice Press, Ca(1986) pp. 292-301.
Takatsuka et al., Proc. IEEE Mar. 1995, Int'l Conference on Microelectronic Test Structures, vol. 8 pp. 247-251.

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