Process for locating physical addresses in a nonuniform...

Details Process for locating physical addresses in a nonuniform... Process for locating physical addresses in a nonuniform...

1999-10-26

2002-06-04

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S205000

Reexamination Certificate

active

06401184

ABSTRACT:

FIELD OF THE INVENTION
The field of application of the invention is that of data processing machines with nonuniform access memory.
DESCRIPTION OF RELATED ART
A memory has nonuniform access when the time interval between the instant at which a request for access to a resource of the memory is sent and the instant at which a response is received varies depending on the location of the resource in the memory. This time interval is called access latency.
One advantage offered by a machine or computer system with nonuniform access memory is the ability to allocate resources in a physical memory of large size to processes executed by the computer system, using a single operating system.
The operating system of the computer manages the physical memory by means of physical addresses in a physical address space. The physical address space is generally subdivided into physical pages of predetermined size. The operating system gives processes access to a virtual address space constituted by segments containing virtual pages that are identical in size to the physical pages. The operating system takes care of mapping each virtual page actually used by a process with a physical page of the memory, using a virtual memory manager.
Virtual memory managers are known within the framework of computers with uniform access memory, in which the location of a physical page, for mapping purposes, does not have any effect on the access latency.
A problem arises in using a known virtual memory manager within the framework of data processing systems with nonuniform access memory in a high-performance manner. In essence, is preferable for a physical page mapped with a virtual page for a given process, insofar as possible, to be a physical page with minimal access latency for the process in question.
It is therefore necessary to be able to locate logical page numbers, or more generally physical addresses, in the nonuniform access memory.
Before the startup of the operating system of the computer, a range of contiguous physical addresses of the physical address space is assigned to each set of resources at the same location in the physical memory.
In order to locate a physical address, a first solution that presents itself consists of comparing the physical address to each address range until the address range that contains it is found, and of thus deducing its location. At best, the first comparison is enough, but at worst, the result is obtained only after comparison with all of the address ranges. Moreover, a comparison with a high-latency address range slows down the obtainment of the result. The process of this first solution is not satisfactory because of the risk that the duration of its implementation will diminish the performance of the machine.
In order to locate a physical address, a second solution that presents itself consists of dividing the value of the physical address by the size of a set of resources. The result provides a resource set order from which it is possible to deduce the location. The process of this second solution is only applicable if all of the resource sets have the same size.
SUMMARY OF THE INVENTION
The subject of the invention is a process that makes it possible to rapidly locate a physical address, no matter what the size of the resource sets at the same location.
According to the invent ion, the process identifies the place of residence of a physical memory resource with a physical address AP in a physical address space associated with a nonuniform access memory MP distributed among several places of residence, one of which is that of said resource. The process comprises:
a preparation step that subdivides the physical address space into physical address sub-spaces of identical size, so as to associate with each place of residence a whole number of physical address sub-spaces;
an identification step that recognizes the physical address sub-space to which the physical address belongs and identifies the place of residence of said resource as being that associated with the recognized address sub-space.


REFERENCES:
patent: 5584004 (1996-12-01), Aimoto et al.
patent: 5784706 (1998-07-01), Fromm et al.
patent: 0 780 770 (1997-06-01), None
patent: 0 817 059 (1998-01-01), None

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